P‐176L: Late‐News Poster: A 3.7Gb/s Clock‐embedded Intra‐Panel Interface for the Large‐sized UHD 120Hz LCD TV Application

Abstract

An Intra-panel interface that supports 3.7Gb/s data transmission on the ultra-high definition (UHD) TV application is proposed. The interface channel of display module for UHD TV consists of long PCB traces and flexible flat cable (FFC), which severely degrade the signal quality of transmitted signal. To support over 3Gb/s data rate in the interface channel of UHD display, the receiver in the column driver is equipped with a continuous-time linear equalizer (CTLE) with adjustable equalization step and data sampler with improved setup and hold time. The transmitter for the proposed interface is implemented using a field programmable gate array (FPGA). The column driver with the proposed receiver is fabricated with a 0.18um high-voltage CMOS process. The proposed interface is verified with 84-inch UHD (3840RGBx2160) resolution TFT-LCD module with 10-bit color depth and 120Hz refresh rate for large-sized TV application. The proposed receiver in the column driver achieves 3.7Gb/s data rate in wafer test and 3.1Gbps data rate that is the maximum data rate in the pattern generator at the LCD module with 80-cm FFC.. Author

P‐29: A 5.4Gbps Intra‐Panel Interface with Advanced Integrated‐Stream Protocol for Thin‐Film Transistor Liquid‐Crystal Display Applications

“…As the data rate or length of signal transmission path increases, signal quality decreases. To improve signal quality, both preemphasis/de-emphasis at the transmitter and continuous-time linear-equalizer (CTLE) at the receiver have been widely used in high-speed serial links to compensate for channel attenuation [2][3].…”

“…The coding rule indicates that the number of maximum continuous bits is five in a packet for RGB data. Thus, the bit state must be changed at least three times per packet, and one of these changes should be: B[0] and B [1] or B [1] and B [2]. All the RGB data streams must follow these rules to ensure that the data format is correct.…”

The Oscillation Frequency of CML-based Multipath Ring Oscillators

“…Therefore, it can run at higher speed than the corresponding inverter-based ring oscillator, whose maximum achievable frequency is highly correlated with the process technology. For example, as high definition (HD), ultra-high definition (UHD) and 8K (Quard-UHD) TVs are being adopted in the television market, the throughput of the intra-panel interface from the timing controller (TCON) to the source-driver IC (SIC) can exceed 10 Gbps, while the SIC circuit process technology is typically limited to 180 nm CMOS because of high voltages needed for pixel driving [4][5][6][7]. To enable the next generation display interface, CML-based ring oscillators running at higher frequency with conventional process technologies are highly desired.…”