Oxide roughness effect on tunneling current of MOS diodes

Abstract

Two-dimensional (2-D) device simulation is used to investigate the tunneling current of metal ultra-thin-oxide silicon tunneling diodes with different oxide roughness. With the conformal nature of ultrathin oxide, the tunneling current density is simulated in both direct tunneling and Fowler-Nordheim (FN) tunneling regimes with different oxide roughness. The results show that oxide roughness dramatically enhances the tunneling current density and the 2-D electrical effect is responsible for this increment of tunneling current density. Furthermore, a set of devices with controlled oxide roughness is fabricated to verify the simulation results and our model qualitatively agrees with the experiment results.

Uniform SiGe/Si quantum well nanorod and nanodot arrays fabricated using nanosphere lithography

“…Many techniques including laser- [40] and metal-assisted [41] chemical etching have been reported to fabricate ‘black silicon’ with an ultra-low reflectance. The surface nanoroughening process in this study could be an alternative approach applied to SiGe-based nanodevices and optoelectronics, such as metal-oxide-Si tunneling diodes [42], light-emitting diodes [25], and photodetectors operating in the telecommunication range [28]. In addition, the SiGe/Si MQW nanopits and nanorods with well-defined spatial periodicity fabricated in this study would also be potential materials applied to photonic crystals [1] and phototransistors [43].…”

Fowler-Nordheim hole tunneling in metal-Er2O3-silicon structures

“…The high average breakdown field indicates good electrical properties and reliability of the film, which are desired for a promising gate dielectric. As we know, the oxide roughness and interface roughness dramatically reduce the breakdown field, 14 the high average breakdown field in Figs. 2 and 3 implies that the film has a very smooth surface as well as a very smooth interface, which is well consistent with our RHEED, AFM, and XRD results.…”

A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs

“…In practice, the gate oxide cannot be reduced below a certain limit because the tunneling current will occur. For example, when the thickness is scaled down below 3 nm [17], the V t;s ¼ gate tunneling leakage caused by the quantum mechanical effects will come about and degrade the device performance.…”