Oxide-based RRAM materials for neuromorphic computing

Hong, XiaoLiang; Loy, Desmond JiaJun; Dananjaya, Putu Andhita; Tan, Funan; Ng, CheeMang; Lew, Wen Siang

doi:10.1007/s10853-018-2134-6

Cited by 218 publications

(178 citation statements)

References 187 publications

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“…For example, in analog matrix-vector multiplication, voltage drops across metal interconnect lines cause computational errors and, therefore, the memristor array size must be limited. Thus, it is essential to demonstrate all the aforementioned properties in nanometer-scale memristors repeatedly and reproducibly.Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. This further benefits the energy and area efficiency by amortizing the costs of anolog to digital converters (ADC) required in the circuit.…”

mentioning

confidence: 99%

“…Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.…”

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confidence: 99%

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Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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in computing accelerators compared to high density storage-class memory, it is frequently important in computing applications to program multiple bits of information within every device by achieving many distinct conductance levels, while keeping the operating currents lower especially at the high conductance states. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy. For example, in analog matrix-vector multiplication, voltage drops across metal interconnect lines cause computational errors and, therefore, the memristor array size must be limited. [6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. This further benefits the energy and area efficiency by amortizing the costs of anolog to digital converters (ADC) required in the circuit. [4] However, existing demonstrations have a narrow dynamic range and achieving multiple low conductance levels is challenging. A larger ratio between the high and low conductances (on/off ratio) helps in achieving more distinct programmable low conductance levels. In addition, memristors are required to be integrated with CMOS circuits in many such applications. For instance, a 1-transistor-1-memristor (1T1M) combination provides in situ current compliance through gate voltage modulation so that the memristor can be programmed in an analog manner. [12,16,25] This brings another challenge: compatibility of memristor and CMOS. This includes not only material and fabrication compatibility, but also CMOS performance meeting the memristor operating requirements as both continue size scaling. Thus, it is essential to demonstrate all the aforementioned properties in nanometer-scale memristors repeatedly and reproducibly.Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.Using memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. Such accelerators have demonstrated the potential to significantly outperform digital computers in highly relevant applications such as machine learning and image processing. However, improvements in device-level performance of memristors, including reducing power consumption and high current-induced metal migration in interconnects, need continued developments. Nanoscaling and complementary metal-oxide semiconductor (CMOS) integration are also of significant ...

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confidence: 99%

mentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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“…OxRAM devices used in this study have larger area, thereby it exhibits higher delay and energy costs. To do a fair comparison with state of the art architectures, we have used device parameters of advanced bilayer filamentary HfOx devices 16,17 (listed in supplementary Table 1). Figure 5(a) highlights the performance comparison for 64-bit Logic operations performed using a conventional CPU (Intel Core i5-2500 Sandy Bridge CPU) and SLIM bitcell assuming data is to be fetched from DRAM/SLIM array.…”

Section: Performance Analysismentioning

confidence: 99%

“…Performance results for edge detection application using conventional and SLIM based system configuration16,17,18,19 .…”

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confidence: 99%

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

Kingra

Parmar

Chang

et al. 2020

Sci Rep

1,267

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Von Neumann architecture based computers isolate/physically separate computation and storage units i.e. data is shuttled between computation unit (processor) and memory unit to realize logic/ arithmetic and storage functions. This to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the memory wall. Logic in-Memory (LIM) approaches aim to address this bottleneck by computing inside the memory units and thereby eliminating the energy-intensive and time-consuming data movement. However, most LIM approaches reported in literature are not truly "simultaneous" as during LIM operation the bitcell can be used only as a Memory cell or only as a Logic cell. The bitcell is not capable of storing both the Memory/Logic outputs simultaneously. Here, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology that allows to implement both Memory and Logic operations simultaneously on the same bitcell in a nondestructive manner without losing the previously stored Memory state. Through extensive experiments we demonstrate the SLIM methodology using non-filamentary bilayer analog OxRAM devices with NMOS transistors (2T-1R bitcell). Detailed programming scheme, array level implementation and controller architecture are also proposed. Furthermore, to study the impact of introducing SLIM array in the memory hierarchy, a simple image processing application (edge detection) is also investigated. It has been estimated that by performing all computations inside the SLIM array, the total Energy Delay Product (EDP) reduces by ~ 40x in comparison to a modern-day computer. EDP saving owing to reduction in data transfer between CPU  Memory is observed to be ~ 780x.Over the past few decades, the performance gap between the computing unit (where the data is processed) and the memory unit (where the data is stored) is increasing, popularly known as the memory wall 1 . It is observed that for many computing tasks, most of the time and energy is consumed in data transfer between the processing unit and memory unit, rather than the computation 2 . To tackle this bottleneck, various solutions have been proposed, targeting from component level to the system architecture level. Measures include the extensive use of spatial architectures (distributed on-chip memory that is closer to the computation unit) enabling parallelism using vector processing unit, with large number of cores 3 . Furthermore, accelerators have been designed to match the exact data flow for specific computing algorithms 4 . Three-dimensional memories, commercialized as hybrid memory cube 5 and high bandwidth memory 6 chips have been proposed to meet the requirements of high data-transfer rate and high memory density. These deliver an order of magnitude higher bandwidth and reduce access energy by up to 5x relative to existing 2-dimensional DRAMs 7 . Moving further, emerging non-volatile memories (NVM) have been introduced into the traditional memory hierarchy to minimize the 'gap' between computing and the data units 8 . However, t...

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“…Memristor is a natural application for resistive random access memory (ReRAM) technology [4]; moreover, neuromorphic computation using ReRAM technology is also becoming popular [2], [5], [6], [7]. By controlling programming signal width and/or amplitude, memristor can be taken to any state; however, two states: high resistance state (HRS) and low resistance state (LRS) are commonly used and they represent bit 1 and bit 0 respectively [2], [8], [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Nonvolatile Memory Cell Based on Memristor

Parajuli¹,

Budhathoki²,

Kim³

2020

ujeee

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Memristor, one of the fundamental circuit elements, has promising applications in non-volatile memory and storage technology as it can theoretically achieve infinite states. Information can be stored independently in these states and retrieved whenever required. In this paper, we have proposed a non volatile memory cell based on memristor emulator. The circuit is able to perform read and write operations. In this memristor based memroy cell, unipolar pulse is used for writing and bipolar pulse is used for reading. Unlike other earlier designs, the circuit does not need external read/write enable switches to switch between read and write operations; the switching is achieved by the zero average bipolar read pulse given after the completion of write cycle. In our proposed memristor based memory cell, single bit can be read and any voltages from 0 to 5 volts can be written. Mathematical analysis and the simulation results of memristor emulator based read write circuit have been presented to confirm its operation.

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Oxide-based RRAM materials for neuromorphic computing

Cited by 218 publications

References 187 publications

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

Nonvolatile Memory Cell Based on Memristor

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