Oxidation effect on the loss characteristics of CPWs implemented on low resistivity substrate with thick Oxidized Porous Silicon (OPS) layer

Ha, Man−Lyun; Shin, Seong‐Ho; Kim, Moon Jung; Ko, Ju-Hyun; Kwon, Young–Se

doi:10.1109/euma.2003.340860

Cited by 1 publication

(3 citation statements)

References 15 publications

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“…Oxidation temperature is shown to reduce attenuation in the OPS film. Attenuation values of 5.25 and 2.5 dB/cm are observed at 18 GHz [11] for oxidation temperature of 1080 o C in the 0.01 ohm-cm material. On the same circuit, when a low oxidization temperature is used similar to the one used to passivate the OCPS, the insertion loss is approximately 2dB higher at 18 GHz for both designs.…”

Section: A Transmission Line Characterizationmentioning

confidence: 88%

“…For passive components in Both OCPS and OPS films have been demonstrated to have quality factor values in the range of 7-20 for lumped inductor elements [11] when the substrate is attached. In the latter OCPS designs, a 6 turn inductor shows a 50% increase in quality factor from 15 to 30 due to the removal of the bulk substrate.…”

Section: B Circuit Demonstrationsmentioning

confidence: 97%

“…CPW lines printed on oxide converted PS (i.e. thick oxide) have been reported in [11] for substrate resistivity values of 0.01 and 8-10 ohm-cm. The two test circuit dimensions of S and W are 100 and 30 for design 1 and 40 and 5 microns for design 2 for matched lines.…”

Section: A Transmission Line Characterizationmentioning

confidence: 99%

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Recent developments in porous silicon substrates for RF/microwave applications

Drayton

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.

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Highly integrated system design is sought in silicon (Si) substrates due to the potential cost savings from volume manufacturing. For GHz applications two research efforts in silicon have evolved, BiCMOS in SiGe and CMOS in Si, that utilize of high and low resistivity silicon materials, respectively. In order to integrate active and passive designs in CMOS grade substrates with conductive and insulating features, multilayer and substrate modification methods have been investigated. This paper will present an overview of one substrate modification method, porous silicon, and recent electrical characterization data of GHz interconnect performance on dielectric capped and oxide converted forms of the material. In addition, highlights of several RF circuit demonstrations will be presented on lumped element, active circuit, and packaging performance.

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Section: A Transmission Line Characterizationmentioning

confidence: 88%

Section: B Circuit Demonstrationsmentioning

confidence: 97%