Overview of the 4S Project

Abstract

-In this paper an overview of the EU-FP6 "Smart Chips for Smart Surroundings" (4S) [7] project is given. The overall mission of the 4S project is to define and develop efficient (ultra low-power), flexible, reconfigurable core building blocks, including the supporting tools, for future ambient systems. Dynamic reconfiguration offers the flexibility and adaptability needed for future ambient devices, it provides the efficiency needed for these systems, it enables systems that can adapt to rapidly changing environmental conditions, it enables communication over heterogeneous wireless networks, and it reduces risks: reconfigurable systems can adapt to standards that may vary from place to place or standards that have changed during and after product development.

Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors

“…10 Model of our multi-core reconfigurable processor [1] In this sub-section, we provide a brief overview of our multi-core reconfigurable processor 5 to the level of detail that is necessary to understand the experimental results. Our results (in comparison with Morpheus [14] and 4S [13]) show that our scheme is generic and is applicable to different kinds of multi-core reconfigurable processors. Fig.…”

“…However, state-of-the-art multi-core reconfigurable processors [1,13,14] do not exploit simultaneous multi-tasking (with both task-and instruction-level parallelism) at their full throttle, when considering the heterogeneous nature of fine-and coarse-grained reconfigurable fabrics and the scenarios of run-time varying task mapping, workload conditions, etc. Moreover, these processors lack efficient fabric allocation schemes that operate with consideration of simultaneous multi-tasking.…”

“…We implemented our scheme for KAHRIMSA [1] and compared the results with state-of-the-art multi-core reconfigurable processors (like 4S [13] and Morpheus [14]) and different task and functional block level fabric allocation policies. For a fair comparison, we have provided the same set of hardware accelerators and ISEs as well as the same amount of memory bandwidth and same input data for each comparison.…”

“…Fig. 12 shows the comparison to multi-core reconfigurable architectures like Morpheus [14] and 4S [13]. These architectures have already proposed solutions for mixed-grained fabric allocation to achieve adaptivity at the task level.…”

“…motion estimation or the actual encoding in case of a video encoder). Typically, reconfigurable architectures use Instruction Set Extensions (ISEs) to accelerate the kernels [1,13,14,22]. These ISEs consist of data-paths that may be reconfigured on parts of a fine-grained (FG) or a coarse-grained (CG) reconfigurable fabric [1,18].…”