Overview of floating-gate devices, circuits, and systems

Hasler, P.; Lande, Tor Sverre

doi:10.1109/tcsii.2001.913180

Cited by 110 publications

(61 citation statements)

References 11 publications

(11 reference statements)

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“…Floating-gate CMOS circuits have found their use outside the digital memory use during the last decade, and an introduction to the field can be found in [1]. Floating-gate devices are used as analog memory elements, as part of capacitivebased circuits and as adaptive circuit elements [1].…”

Section: Introductionmentioning

confidence: 99%

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Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware

Aunet

Hartmann

2003

Evolvable Systems: From Biology to Hardware

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Abstract. This paper discusses some aspects regarding the use of universal linear threshold elements implemented in a standard double-poly CMOS technology, which might be used for neural networks as well as plain, or mixed-signal, analog and digital circuits. The 2-transistor elements can have their threshold adjusted in real time, and thus the basic Boolean function, by changing the voltage on one or more of the inputs. The proposed elements allow for significant reduction in transistor count and number of interconnections. This in combination with a power supply voltage in the range of less than 100 mV up to typically 1.0 V allow for Power-Delay-product improvements typically in the range of hundreds to thousands of times compared to standard implementations in a 0.6 micron CMOS technology. This makes the circuits more similar to biological neurons than most existing CMOS implementations. Circuit examples are explored by theory, SPICE simulations and chip measurements. A way of exploiting inherit fault tolerance is briefly mentioned. Potential improvements on operational speed and chip area of linear threshold elements used for perceptual tasks are shown.

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Section: Introductionmentioning

confidence: 99%

“…Floating-gate devices are used as analog memory elements, as part of capacitivebased circuits and as adaptive circuit elements [1]. Non-traditional floating-gate circuitry is also starting to find it's way into commercial use [2].…”

Section: Introductionmentioning

confidence: 99%

Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware

Aunet

Hartmann

2003

Evolvable Systems: From Biology to Hardware

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“…Implementation of the floating-gate potential, V FG , can be made via a variety of different methods. For true floating-gates, hot-electron injection, electron tunnelling or UV-exposure is normally used [3], [10], [11]. If the CMOS process also has a gateoxide thickness of 70Å or less [7], some kind of refresh or auto-biasing technique is also required as gate charge leakage will be significant [8].…”

Section: Fgmos Basicsmentioning

confidence: 99%

“…One of the ways to reduce power is to explore new types of circuits in order to find better circuit techniques for energy savings. Floating-gate MOS (FGMOS) is a circuit technique that has been proposed in several previous works as a potentially good technique to reduce power consumption and still maintain a relatively high speed [1], [2], [3]. FGMOS is normally fabricated using a standard CMOS process where an extra floating-gate capacitance is connected to the transistor's gate node.…”

Section: Introductionmentioning

confidence: 99%

“…This capacitance, called floating-gate capacitance, will make it possible to shift the threshold voltage level of the MOS-transistors. The required effective threshold voltage for the gate will thereby change and the shift is controlled by the floating-gate's node charge voltage [1], [3]. A shift in threshold voltage will also change the static current (and power consumption), normally to a higher value, at the same time as the propagation delay of the circuit will be different (normally smaller).…”

Section: Introductionmentioning

confidence: 99%

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Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply

Alfredsson

Aunet

Lecture Notes in Computer Science

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Abstract. To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS fulladder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

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