Overview of Advanced 3D Charge-trapping Flash Memory Devices

Abstract

Although conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore's law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.

Inert ambient annealing effect on MANOS capacitor memory characteristics

“…The scaling continuation of the standard floating gate memory devices confronts significant difficulties, most prominent of which are the maintenance of the gate capacitance coupling ratio and the electrostatic interference between the adjacent memory cells [1][2][3][4]. MANOS (metal, alumina, silicon nitride silicon dioxide, silicon) constitutes at present a promising solution that may enable the successful realization of three-dimensional integration of non-volatile memories [5]. MANOS was proposed as a modification of the standard SONOS (silicon, silicon dioxide, silicon nitride, silicon dioxide, silicon) charge trapping (CT) device [6][7][8], where an Al 2 O 3 layer is utilized as a blocking layer [9].…”

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

“…reducing tunnelling oxide thickness and using high-k dielectrics, without compromising on reliability and endurance, 3 as there are formidable challenges associated with physical scaling of devices, such as cell-to-cell interference, poor reliability and lower gate coupling ratio. [3][4][5][6][7][8] The use of charge trapping layers, encased in a high-k dielectric, 9,10 as storage nodes is the most promising route to overcome these issues. 8 Charge trapping devices, comprising of either interface traps or nanoparticles as storage nodes have been studied for a long time, [11][12][13] especially for military and space applications due to their enhanced radiation tolerance.…”

“…[3][4][5][6][7][8] The use of charge trapping layers, encased in a high-k dielectric, 9,10 as storage nodes is the most promising route to overcome these issues. 8 Charge trapping devices, comprising of either interface traps or nanoparticles as storage nodes have been studied for a long time, [11][12][13] especially for military and space applications due to their enhanced radiation tolerance. [14][15][16] ONO (oxide nitride oxide) stacks, semiconductor nanoparticles, and metal nanoparticles have been mainly studied as charge trapping layers.…”