Overhead and Performance Comparison of SET Fault Tolerant Circuits Used in Flash-based FPGAs

Abstract

The aim of alternative fault tolerant techniques used in flash-based FPGAs, such as Single Event Transient (SET) filters, is to provide a resource savings advantage when compared to Triple Modular Redundancy (TMR). The purpose of this paper is to quantify, in terms of particular circuit characteristics, what the savings will be. The results suggest that the most important circuit characteristic to determine the gate count increase is the ratio of the number of primary outputs to the original circuit gate count, when considering a combinational circuit. When considering a sequential circuit, the most important circuit characteristic is the ratio of the number of Register Logic (RL) vs. Combinational Logic (CL) in the datapath. The theoretical study found that the DMR and delay element Guard Gate (GG) SET filter technique used in sequential circuits, proved more costly than TMR in terms of resource increase, when the ratio of the number of RL vs. CL is greater than 10% and 28% respectively. Chip-level synthesis of circuits using these filter techniques with one family of flash-based FPGAs shows no gate count cost benefit compared to TMR when the ratio of the number of RL vs. CL is greater than 13% and 15% respectively.