Overcoming scaling barriers through design technology CoOptimization

Liebmann, Lars W.; Zeng, Jia; Zhu, Xingyi; Yuan, Ling; Bouche, G.; Kye, Jongwook

doi:10.1109/vlsit.2016.7573398

Cited by 37 publications

(13 citation statements)

References 2 publications

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“…Similar trends are also observed for N7 b . Curve "CNN" denotes training the CNN of 5 layers in Figure 11(a) with data from target domain only, i.e., no 2 Results for active learning extended from [41] CNN CNN TF 0 ResNet TF 0 ResNet TF 4 ResNet TF 6 ResNet TF 8 ResNet TF 0 +AL 2 1 10 20 30 40 50 transfer learning involved. Curve "CNN TF0" denotes the transfer learning scheme in Section III-D for the same CNN with zero layer fixed.…”

Section: B Knowledge Transfer From N10 To N7mentioning

confidence: 99%

“…Due to the continuous semiconductor scaling from 10nm technology node (N10) to 7nm node (N7) [1], [2], the prediction of printed pattern sizes is becoming increasingly difficult and complicated due to the complexity of manufacturing process and variations. However, complex designs demand accurate simulations to guarantee functionality and yield.…”

Section: Introductionmentioning

confidence: 99%

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Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection

Lin

Watanabe

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Lithography simulation is one of the key steps in physical verification, enabled by the substantial optical and resist models. A resist model bridges the aerial image simulation to printed patterns. While the effectiveness of learning-based solutions for resist modeling has been demonstrated, they are considerably data-demanding. Meanwhile, a set of manufactured data for a specific lithography configuration is only valid for the training of one single model, indicating low data efficiency. Due to the complexity of the manufacturing process, obtaining enough data for acceptable accuracy becomes very expensive in terms of both time and cost, especially during the evolution of technology generations when the design space is intensively explored. In this work, we propose a new resist modeling framework for contact layers, utilizing existing data from old technology nodes and active selection of data in a target technology node, to reduce the amount of data required from the target lithography configuration. Our framework based on transfer learning and active learning techniques is effective within a competitive range of accuracy, i.e., 3-10X reduction on the amount of training data with comparable accuracy to the state-of-the-art learning approach.

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Section: B Knowledge Transfer From N10 To N7mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection

Lin

Watanabe

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…To continue Moore's law, transistor sizes are scaled down to the 7 nm node (N7) and 5 nm node (N5) specifications [15,16]. A contacted gate pitch (CGP) of 42 and 32 nm were used in both the N7 and N5 devices.…”

Section: Gaa-nw Devicementioning

confidence: 99%

“…Considering a fixed NW pitch (NWP) of 14 and 10 nm offset, the two-stacked-NW device creates a fin height of 31 and 29 nm, respectively. Other specifications and setup for each device were considered similar to the reference [10,15]. The simulated compact NW is shown in…”

Section: Gaa-nw Devicementioning

confidence: 99%

Parasitic Capacitances on Scaling Lateral Nanowire

Das¹,

Bhattacharyya²

2019

Nanowires - Synthesis, Properties and Applications

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The gate-all-around silicon nanowire transistor (GAA-NW) has manifested itself as one of the most fortunate candidates for advanced node integrated circuits (ICs). As the GAA transistor has stronger gate control, better scalability, as well as improved transport properties, the device has been considered as a potential alternative for scaling beyond FinFET. In recent publications, the basic feature and scalability of nanowire have been widely explored primarily focusing on intrinsic device characteristics. Although the GAA-NW has superior gate control compared to other architectures, the device is surrounded by huge vertical gate metal line and S/D contact metal lines. The presence of this vast metal line forms a strong parasitic capacitance. While scaling down sub-7 nm node dimensions, these capacitances influence strongly on the overall device performances. In this chapter, we have discussed the effects of various parasitic capacitances on scaling the device dimensions as well as their performances at high-frequency operations. TCADbased compact model was used to study the impacts of scaling GAA-NW's dimensions on power performance and area gain perspective (PPA).

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“…Specifically, the SC layout design is restricted within a fixed height, i.e., SC architecture, which incurs large turnaround time for transistor-level placement and routing in a human-driven procedure. This further leads to a wide research domain of design technology co-optimization (DTCO) [3,4], which is beyond the scope of SC library design and optimization methodology in this study.…”

Section: Introductionmentioning

confidence: 99%

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)

Shah

Evans

et al. 2017

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Standard cell libraries are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and beyond, standard cell library design and optimization is becoming increasingly di cult due to extremely complex design constraints, as described in the ASAP7 process design kit (PDK). Notable complexities include discrete transistor sizing due to FinFETs, complicated design rules from lithography and restrictive layout space from modern standard cell architectures. The design methodology presented in this paper enables e cient and high-quality standard cell library design and optimization with the ASAP7 PDK. The key techniques include exhaustive transistor sizing for cell timing optimization, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations.

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Overcoming scaling barriers through design technology CoOptimization

Cited by 37 publications

References 2 publications

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection

Parasitic Capacitances on Scaling Lateral Nanowire

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)

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