Overcoming DRAM scaling limitations by employing straight recessed channel array transistors with &amp;gt;100&amp;lt; uni-axial and [100] uni-plane channels

Kim, I.-G.; Park, S.-H.; Yoon, Jae-Man; Kim, D.-J.; Noh, Jinhyun; Lee, J.-H.; Kim, Y.-S.; Hwang, Moon-Sang; Yang, K. H.; Park, Joosung; Oh, Kyungseok

doi:10.1109/iedm.2005.1609339

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Overcoming DRAM scaling limitations by employing straight recessed channel array transistors with >100< uni-axial and [100] uni-plane channels

Cited by 4 publications

References 1 publication

Analysis of Intermittent Single-bit Failure on 10-nm node generation DRAM Devices

Analysis of Intermittent Single-bit Failure on 10-nm node generation DRAM Devices

DRAM World-line Bottom Roughness Detection Using BSE Signal

A Semi-Floating Gate Transistor with Enhanced Embedded Tunneling Field Effect Transistor

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