Overall consideration of scan design and test generation

Chen, Guihai; Liu, Ming; Wang, Hong

doi:10.1109/iccad.1992.279407

Cited by 26 publications

(1 citation statement)

References 13 publications

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“…In Ref. 88, specific hardware that varies the number of FFs controlled and observed by the scan shift operation from 1 to n (the number of FFs in the circuit under test) has been proposed. For example, in one mode, only one FF is controlled and observed, and in another mode, two FFs are controlled and observed.…”

Section: Methods For Circuits With a Single Scan Chainmentioning

confidence: 99%

Test cost reduction for logic circuits: Reduction of test data volume and test application time

Higami

Kajihara

Ichihara

et al. 2005

Systems & Computers in Japan

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SUMMARYWe believe that reduction of the testing cost is becoming increasingly important as the size of VLSIs becomes larger. Moreover, as the structure of VLSIs becomes more complicated, test compaction, test compression, and test application time reduction for non-stuck-at faults, such as delay faults, bridging faults, crosstalk faults, and open faults, must be considered. In addition, new methods of fault diagnosis and high-level testing must be developed in order to reduce testing costs or diagnostic costs. In this paper we have surveyed recent research on the reduction of testing cost for logic circuits, including test compaction for combinational circuits and sequential circuits, test compaction under IDDQ testing, and test compression and test application time reduction for scan circuits.

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Section: Methods For Circuits With a Single Scan Chainmentioning

confidence: 99%