Over one million TPCC with a 45nm 6-core Xeon&amp;#x00AE; CPU

Kuppuswamy, Ravi; Sawant, Shankar; Balasubramanian, S.; Kaushik, P.; Natarajan, Nagarajan; Gilbert, Jeffrey D.

doi:10.1109/isscc.2009.4977312

Cited by 13 publications

(4 citation statements)

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“…We updated the energy parameters to a 45nm technology based on technology scaling rules. We also estimate processor power consumption using IPC-based linear scaling of the maximum power consumption of a 45nm Intel Xeon [22], as suggested in [3]. The estimates of the two power models closely matched one another.…”

Section: Discussionmentioning

confidence: 87%

Virtualized and flexible ECC for main memory

Yoon

Erez

2010

SIGARCH Comput. Archit. News

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We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We rely on this basic idea, which increases flexibility to increase error protection capabilities, improve power efficiency, and reduce system cost; with only small performance overheads. We augment the virtual memory system architecture to detach the physical mapping of data from the physical mapping of its associated ECC information. We then use this mechanism to develop two-tiered error protection techniques that separate the process of detecting errors from the rare need to also correct errors, and thus save energy. We describe how to provide strong chipkill and double-chip kill protection using existing DRAM and packaging technology. We show how to maintain access granularity and redundancy overheads, even when using ×8 DRAM chips. We also evaluate error correction for systems that do not use ECC DIMMs. Overall, analysis of demanding SPEC CPU 2006 and PARSEC benchmarks indicates that performance overhead is only 1% with ECC DIMMs and less than 10% using standard Non-ECC DIMM configurations, that DRAM power savings can be as high as 27%, and that the system energy-delay product is improved by 12% on average.

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Section: Discussionmentioning

confidence: 87%

Virtualized and flexible ECC for main memory

Yoon

Erez

2010

SIGARCH Comput. Archit. News

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“…The number of on-die thermal sensors keeps growing in very large scale integration (VLSI) systems to enable the DTM of chip functionalities [ 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ], as shown in Figure 1 . The accuracy of on-chip sensor readings has a great influence on the effectiveness and reliability of DTM.…”

Section: Introductionmentioning

confidence: 99%

On-Line Temperature Estimation for Noisy Thermal Sensors Using a Smoothing Filter-Based Kalman Predictor

et al. 2018

Sensors

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Dynamic thermal management (DTM) mechanisms utilize embedded thermal sensors to collect fine-grained temperature information for monitoring the real-time thermal behavior of multi-core processors. However, embedded thermal sensors are very susceptible to a variety of sources of noise, including environmental uncertainty and process variation. This causes the discrepancies between actual temperatures and those observed by on-chip thermal sensors, which seriously affect the efficiency of DTM. In this paper, a smoothing filter-based Kalman prediction technique is proposed to accurately estimate the temperatures from noisy sensor readings. For the multi-sensor estimation scenario, the spatial correlations among different sensor locations are exploited. On this basis, a multi-sensor synergistic calibration algorithm (known as MSSCA) is proposed to improve the simultaneous prediction accuracy of multiple sensors. Moreover, an infrared imaging-based temperature measurement technique is also proposed to capture the thermal traces of an advanced micro devices (AMD) quad-core processor in real time. The acquired real temperature data are used to evaluate our prediction performance. Simulation shows that the proposed synergistic calibration scheme can reduce the root-mean-square error (RMSE) by 1.2 • C and increase the signal-to-noise ratio (SNR) by 15.8 dB (with a very small average runtime overhead) compared with assuming the thermal sensor readings to be ideal. Additionally, the average false alarm rate (FAR) of the corrected sensor temperature readings can be reduced by 28.6%. These results clearly demonstrate that if our approach is used to perform temperature estimation, the response mechanisms of DTM can be triggered to adjust the voltages, frequencies, and cooling fan speeds at more appropriate times.

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“…On the other hand, with the aim of hiding, as much as possible, the huge memory latencies that current DRAM memories present, many commercial processors implement large Last Level Caches (LLC) and other microarchitectural mechanisms like prefetching or simultaneous multithreading. As an example, Figure 1 presents a memory hierarchy of the eight-core IBM Power 5 processor [4], which closely resembles the scheme followed by some processors like Intel Dunnington [5].…”

Section: Introductionmentioning

confidence: 99%

Cache-Hierarchy Contention-Aware Scheduling in CMPs

Feliu

Petit

Sahuquillo

et al. 2014

IEEE Trans. Parallel Distrib. Syst.

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Abstract-In order to improve CMP performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multi-level cache hierarchies that are shared by several multithreaded cores. In this microprocessor design, contention points may appear along the whole memory hierarchy. Moreover, this problem is expected to aggravate in future technologies, since the number of cores and hardware threads, and consequently the size of the shared caches increases with each microprocessor generation. This paper characterizes the impact on performance of the different contention points that appear along the memory subsystem. The analysis shows that some benchmarks are more sensitive to contention in higher levels of the memory hierarchy (e.g., shared L2) than to main memory contention. In this paper we propose two generic scheduling strategies for CMPs. The first strategy takes into account the available bandwidth at each level of the cache hierarchy. The strategy selects the processes to be co-scheduled and allocates them to cores in order to minimize contention effects. The second strategy also considers the performance degradation each process suffers due to contention aware scheduling. Both proposals have been implemented and evaluated in a commercial single-threaded quad-core processor with a relatively small two-level cache hierarchy. The proposals reach, on average, a performance improvement by 5.38% and 6.64% when compared with the Linux scheduler while this improvement is by 3.61% for an state-of-the-art memory-contention aware scheduler under the evaluated mixes.

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Over one million TPCC with a 45nm 6-core Xeon® CPU

Cited by 13 publications

References 1 publication

Virtualized and flexible ECC for main memory

Virtualized and flexible ECC for main memory

On-Line Temperature Estimation for Noisy Thermal Sensors Using a Smoothing Filter-Based Kalman Predictor

Cache-Hierarchy Contention-Aware Scheduling in CMPs

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