OTA-based neural network architectures with on-chip tuning of synapses

Ghosh, Joydeep; LaCour, Pat; Jackson, Steven

doi:10.1109/82.275661

Cited by 8 publications

(6 citation statements)

References 13 publications

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“…(1), the synaptic products Wji. Xi are implemented by using an OTA-based circuit [14], [28] (see below); 9 in Eq. (2), the neuron activation function is implemented by means of a shunt-shunt feedback amplifier [29]; 9 in Eq.…”

Section: Circuit Design Of Computational Primitivesmentioning

confidence: 99%

“…Among the possible hardware implementations of neural networks (through dedicated circuits, either digital or analog), some researchers [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] have pointed out the advantages (i.e., small area and low power consuption) of analog VLSI solutions and have evidenced the possibility of implementing a sufficiently large, efficient and fast system to be used for real world applications. In particular, Mead [2,3] acknowledged that the computational power of biological neural networks results not only from massive parallelism but also from analog processing.…”

Section: Introductionmentioning

confidence: 99%

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An experimental analog VLSI neural network with on-chip back-propagation learning

Valle

Caviglia

Bisio

1996

Analog Integr Circ Sig Process

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Analog VLSI implementations of artificial neural networks are usually considered efficient for the small area and the low power consumption they require, bat very poor in terms of programmability. In this paper, we present an approach to the design of analog VLSI neural information-processing systems with on-chip learning capabilities. We describe a set of analog circuits for implementing the neural computational primitives of a MultiLayer Perceptron, including the ones supporting a gradient-based learning algorithm (Back Propagation). Only supervision tasks are managed off chip.An experimental chip has been designed and fabricated using a standard digital 1.5/zm CMOS N-well technology. The chip contains 4 neurons and 32 synapses organized into a single-layer architecture with 8 inputs and 4 outputs. Measures illustrating the chip behavior during learning are reported.

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Section: Circuit Design Of Computational Primitivesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An experimental analog VLSI neural network with on-chip back-propagation learning

Valle

Caviglia

Bisio

1996

Analog Integr Circ Sig Process

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“…In fact, it is well know that the use of OTA circuit is a very efficient solution for the implementation of a neural network [7].…”

Section: Introductionmentioning

confidence: 99%

“…There are a number of techniques that can be used to reduce the effect of mismatch in analog circuits [ll], [7], [12]. In the particular case of analog implementation of neural network a different strategy can be proposed.…”

Section: Introductionmentioning

confidence: 99%

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VLSI implementation of a modular and programmable neural architecture

Cardarilli

D'Alessandro

Marinucci

et al.

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems

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A mixed-signal VLSI chip architecture f o r multilayer feed-forward neural network implementation with digitally programmable synapses is presented. The chip realizes a fully connected single-layer network, configurable as a 48 input/48 output neurons with 2304 5-bit synapses or as a 24 anput/24 output neurons with 1152 9-bit synapses. This single layer network can be reconfigured as a multi-layer network. Another important chip feature is the possibility of connecting the chips in order to obtain a more complex multi-layer neural network. The core of our architecture is a very eficient circuit block, quoted as "Distributed Sigmoid-Synapse", that we used to implement each of the 2304 5-bit synapses included in the programmable neural network. A prototyping chip, including all the basic block of neural architecture, is now processed b y ES2 with 1.0 pm CMOS technology, Finally, we report the architecture of a possible setup system for the evaluation of the VLSI chip performances. Parameter mismatches present in the chip were considered to be not critical because it is possible to account them during the training of the neural network b y using a special chip-in-the-loop training algorithm. We planned to use this chip in pattern recognition and image processing applications.

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