Oscillator phase noise: a tutorial

Lee, T.H.

doi:10.1109/cicc.1999.777309

Cited by 129 publications

(206 citation statements)

References 7 publications

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“…Increasing the signal power improves the signal/noise ratio simply because the thermal noise is fixed. According to the theory of the impulse sensitivity function (ISF) [15], the current noise charges the tank's capacitor, and the developed voltage across the capacitor modulates the phase of oscillator and the phase noise is proportional to the last term 20 log(∆ω/ω o ). The modulation is a mixing process leading to the AM-PM conversion.…”

Section: Measurement Resultsmentioning

confidence: 99%

Quadrature Vco Formed With Two Colpitts Vco Coupled via an Lc-Ring Resonator

Jang¹,

Lin²,

Chang³

et al. 2011

PIER C

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Abstract-This paper presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two p-core Colpitts cross-coupled voltage-controlled oscillators (VCOs) with an LC ring resonator to provide the quadrature outputs. The proposed CMOS QVCO has been implemented with the TSMC 0.18 µm CMOS technology and the die area is 0.478×0.82 mm 2 . At the supply voltage of 1.5 V, the total power consumption is 20.4 mW. The free-running frequency of the QVCO is tunable from 9.69 GHz to 10.52 GHz as the tuning voltage is varied from 0.0 V to 2 V. The measured phase noise at 1 MHz frequency offset is −122.41 dBc/Hz at the oscillation frequency of 10.52 GHz and the figure of merit (FOM) of the proposed QVCO is −189.7 dBc/Hz.

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Section: Measurement Resultsmentioning

confidence: 99%

Quadrature Vco Formed With Two Colpitts Vco Coupled via an Lc-Ring Resonator

Jang¹,

Lin²,

Chang³

et al. 2011

PIER C

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“…A typical oscillator phase noise spectrum is shown in Figure 8.1 [180]. From it, three different regions can be identified; in the vicinity of the carrier (small ∆ f ) the noise power is proportional to 1/∆ f 3 .…”

Section: Jitter Sourcesmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…As mentioned earlier, the transistor mainly contribute to the overall phase noise in an oscillator and the dominant noise sources of the transistor are often cyclostationary. For instance, the collector current shot noise of a bipolar transistor and the channel noise of a MOS device are cyclostationary [5,6]. Fortunately, the LTV model developed by Hajimiri and Lee is able to accommodate a cyclostationary noise source with ease.…”

Section: Brief Review Of Phase Noise Existing Modelsmentioning

confidence: 99%

“…9), in other words, where the ISF is close to zero (Fig. 10) i.e., when the noise to phase noise conversion is at a minimum [5,9]. Nevertheless, this impulse of current is clearly shorter in the case (c) than in the cases (a) and (b) which clearly demonstrate that the oscillator operating in class-C presents a smaller value of its effective ISF than that of the oscillator operating in a low or maximum power added state as clearly shown in Fig.…”

Section: Influence Of the Amplifier Operating Pointmentioning

confidence: 99%

“…Consequently, Γ e f f , rms needs to be minimized in order to reduce phase noise significantly. In other words, the transistor would remain off almost all of the time, waking up periodically to deliver an impulse of current at the signal peak of the oscillator, where the ISF (Γ(x)) has its minimum value, i.e., when the noise to phase noise conversion is at a minimum [5,9]. Thus, the transistor must be operated in class-C under oscillation conditions in order to reduce significantly the phase noise due to the cyclostationary noise sources.…”

Section: Brief Review Of Phase Noise Existing Modelsmentioning

confidence: 99%

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Minimum phase noise of an LC oscillator: Determination of the optimal operating point of the active part

Cordeau¹,

Paillot²

2010

AEU - International Journal of Electronics and Communications

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In this paper, we describe an original method for determining the optimal operating point of the active part (transistor) of an LC oscillator leading to the minimum phase noise for given specifications in terms of power consumption, oscillation frequency and for given devices (i.e., transistor and resonator). The key point of the proposed method is based on the use of a proper LC oscillator architecture providing a fixed loaded quality factor for different operating points of the active part within the oscillator. The feedback network of this architecture is made of an LC resonator with coupling transformers. In these conditions, we show that it is possible to easily change the operating point of the amplifier, through the determination of the turns ratio of those transformers, and observe its effect on phase noise without modifying the loaded quality factor of the resonator. The optimal operating point for minimum phase noise is then extracted from nonlinear simulations. Once this optimal behaviour of the active part known and by associating the previous LC resonator, a design of an LC oscillator or VCO with an optimal phase noise becomes possible. The conclusions of the presented simulation results have been widely used to design and implement a fully integrated, LC differential VCO on a 0.35 µm BiCMOS SiGe process.

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Oscillator phase noise: a tutorial

Cited by 129 publications

References 7 publications

Quadrature Vco Formed With Two Colpitts Vco Coupled via an Lc-Ring Resonator

Quadrature Vco Formed With Two Colpitts Vco Coupled via an Lc-Ring Resonator

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Minimum phase noise of an LC oscillator: Determination of the optimal operating point of the active part

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