Origin of instability by positive bias stress in amorphous Si-In-Zn-O thin film transistor

Kim, Do-Hyung; Yoo, Dong Youn; Jung, Hyun Kwang; Kim, Dae Hwan; Lee, Sang Yeol

doi:10.1063/1.3657511

Cited by 22 publications

(8 citation statements)

References 15 publications

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“…It has been reported that in oxide-based TFTs, like a-IGZO TFTs, a-SIZO TFTs, a-HIZO TFTs, the origin of V th instability under negative bias illumination stress and positive gate-bias stress is O V defects within the bulk channel and at the channel/ dielectric interface, which trap holes or electrons. 14,20,21 For example, there is a report that the stability of a-SIZO TFTs under PBS is apparently improved as the O V defects within the device channel decrease. 21 Therefore, by comparing the LFN and the XPS results, the major interfacial trap states within the IGZO TFTs are likely O V -related defects.…”

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confidence: 99%

“…14,20,21 For example, there is a report that the stability of a-SIZO TFTs under PBS is apparently improved as the O V defects within the device channel decrease. 21 Therefore, by comparing the LFN and the XPS results, the major interfacial trap states within the IGZO TFTs are likely O V -related defects. In addition, since the interface quality is improved by nitrogen doping, ideally the l FE of the a-IGZO TFTs should increase due to the reduced interface scattering.…”

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confidence: 99%

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Enhanced bias stress stability of a-InGaZnO thin film transistors by inserting an ultra-thin interfacial InGaZnO:N layer

Huang

et al. 2013

Applied Physics Letters

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confidence: 99%

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confidence: 99%

Enhanced bias stress stability of a-InGaZnO thin film transistors by inserting an ultra-thin interfacial InGaZnO:N layer

Huang

et al. 2013

Applied Physics Letters

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“…The positive threshold voltage shift of the n-channel TFTs under the positive gate bias stress had been reported, which was attributed to the electron trapping at the interface between active layer and dielectric layer or in dielectric. 27,28 At the same time, a negative gate bias or negative gate bias with light illumination can cause a negative threshold voltage shift for the n-channel TFTs because of the electron detrapping or hole trapping. 20,29 However, the reported V TH shift behavior is opposite to what is observed in our study.…”

Section: Resultsmentioning

confidence: 99%

“…With this reason, the TFT with N 2 O plasma-treated MgO dielectric exhibits only a small positive V TH after PBS, which is due to the electron trapping at the ZnO/MgO interface. 27,28 After the subsequent NBIS for 3 to 10, the trapped electrons are detrapped and make the V TH return to ∼zero. With increase the duration of NBIS to 50, oxygen ions at ZnO/MgO interface are driven to ZnO film to annihilate some oxygen vacancies and successively decrease free carriers.…”

Section: Resultsmentioning

confidence: 99%

Suppression of Oxygen Vacancy and Enhancement in Bias Stress Stability of High-Mobility ZnO Thin-Film Transistors with N₂O Plasma Treated MgO Gate Dielectrics

Chen

Jeng

2013

ECS J. Solid State Sci. Technol.

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ZnO thin-film transistors (TFTs) using MgO dielectrics achieve a high field-effect mobility of around 50 cm 2 /Vs. Plasma treatments with different gases applied on the MgO dielectric surface will amend the TFT's electrical stability and X-ray photoelectron spectroscopy analysis is done nearby the ZnO/MgO interface to study the change of oxygen chemical bonding states. The results show that MgO dielectric without plasma treatment causes the threshold voltage shift of the transistor, which may be attributed to the migration of oxygen ion toward the ZnO/MgO interface to induce the generation of oxygen vacancies in ZnO active layer when devices are under positive gate bias stress. This instability behavior can be eliminated with N 2 O plasma treatment on MgO. N 2 O plasma treatment inhibits the generation of oxygen vacancies in ZnO against gate bias stress thus reduces the effective trap state density in the subgap of ZnO and thereby enhances the TFT's stability. The detailed scenario for the plasma treatment effect is explored to conclude its mechanism on improving the electrical stability.ZnO is a oxide semiconductor which can be applied to many different electronic devices, such as transparent conducting oxide (TCO), 1,2 light emitting diodes (LED) 3 or resistance random access memory (RRAM). 4,5 Especially, the ZnO-based TFTs 6-11 have attracted attention for application in flat panel display owing to their reasonable mobility and transparency in visible light region. For practical applications, the electrical stability of TFTs will be an important issue to overcome. Bias stress test is a general method to determine the electrical stability of the device by tracing the transfer characteristic (I D -V G curves) of the transistor with giving a constant bias in gate electrode for a period of time. The threshold voltage shift ( V TH ) under gate bias stress is a crucial parameter to determine the electrical stability of TFT devices in active matrix liquid crystal display applications since the bias stress-induced threshold voltage shift leads to a change in the individual pixel brightness. At the same time, V TH that is sensitive to light illumination will limit the TFT application to the next generation of transparent electronics because the exposure of switching TFTs to backlight or ambient light would be inevitable during the operation of the electronics such as display panel. The degradation behaviors of ZnO-based TFTs have been investigated by many previous studies. 12-17 They indicated that the V TH under bias stress or light illumination can be attributed to the charge trapping in the gate insulator or in the active layer/insulator interface, 13-15 and oxygen or water absorption/desorption at back channel. 16,17 In a-Si:H TFTs, the charge trapping sites can be eliminated through an annealing of the a-Si. However, high temperature annealing of ZnO 18 is not suitable for glass substrates owing to their low softening/melting temperatures. 19 An alternative solution for reducing the trapping sites is adding an el...

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“…Zn is easily soluble in weak acids, which is bad for the back‐channel‐etch process. Silicon has been proven to be an excellent dopant for InO x ‐based TFTs, such as InSiO , InZnSiO , and InSnSiO , nevertheless, silicon‐doped indium‐free tin oxide‐based TFTs has not been reported. Because of the different main content of the base channel material, it is necessary to explore the effect of silicon doping on the performance of tin oxide TFTs.…”

Section: Introductionmentioning

confidence: 99%

Effects of silicon doping on the performance of tin oxide thin film transistors

Yang

Zhao

Tao

et al. 2015

Phys. Status Solidi A

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Thin film transistors (TFTs) with silicon‐doped tin oxide (TSO) as channel layer were prepared by radio frequency magnetron sputtering. The decreased defect‐state‐related peak in photoluminescence (PL) excitation spectra and oxygen‐vacancy‐related O 1s peak in X‐ray photoelectron spectroscopy (XPS) with increasing Si content, accompanied by the decreased off‐state current and positive shift of turn‐on voltage, confirms that silicon can be a good carrier suppressor. The optimum TFT performance after annealing at 300 °C was achieved at Si content 5.4 at.%, with saturation mobility of 5.3 cm2 V−1 s−1, turn‐on voltage of −0.2 V, and on‐off current ratio of 3.3 × 106, respectively. Increasing the annealing temperature is useful to improve the mobility, but the polycrystalline structure formed above 350 °C goes against the uniformity of oxide TFTs.

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Origin of instability by positive bias stress in amorphous Si-In-Zn-O thin film transistor

Cited by 22 publications

References 15 publications

Enhanced bias stress stability of a-InGaZnO thin film transistors by inserting an ultra-thin interfacial InGaZnO:N layer

Enhanced bias stress stability of a-InGaZnO thin film transistors by inserting an ultra-thin interfacial InGaZnO:N layer

Suppression of Oxygen Vacancy and Enhancement in Bias Stress Stability of High-Mobility ZnO Thin-Film Transistors with N₂O Plasma Treated MgO Gate Dielectrics

Effects of silicon doping on the performance of tin oxide thin film transistors

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Origin of instability by positive bias stress in amorphous Si-In-Zn-O thin film transistor

Cited by 22 publications

References 15 publications

Enhanced bias stress stability of a-InGaZnO thin film transistors by inserting an ultra-thin interfacial InGaZnO:N layer

Enhanced bias stress stability of a-InGaZnO thin film transistors by inserting an ultra-thin interfacial InGaZnO:N layer

Suppression of Oxygen Vacancy and Enhancement in Bias Stress Stability of High-Mobility ZnO Thin-Film Transistors with N2O Plasma Treated MgO Gate Dielectrics

Effects of silicon doping on the performance of tin oxide thin film transistors

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Suppression of Oxygen Vacancy and Enhancement in Bias Stress Stability of High-Mobility ZnO Thin-Film Transistors with N₂O Plasma Treated MgO Gate Dielectrics