Organization of the TRAC processor-memory subsystem

Kapur, Rajan N.; Premkumar, U. V.; Lipovski, G. Jack

doi:10.1145/1500518.1500622

Cited by 14 publications

(3 citation statements)

References 5 publications

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“…A virtual machine that would be ideal for the algorithms here consists of a network of processors organized as a complete graph with one cell per processor. More realistically, a system of processors communicating through a high bandwidth switching network, such as in the TRAC system (Kapur, Lipovski, Premkumar 1980) or PASM (Siegel. 1979) could be used, with grid cells mapped onto these processors in a many to one manner.…”

Section: Architecturementioning

confidence: 99%

Parallel Architectures for Iterative Methods on Adaptive, Block Structured Grids

Gannon¹,

Vanrosendale²

1984

Elliptic Problem Solvers

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This paper proposes a parallel computer architecture well suited to the solution of partial differential equations in complicated geometries.Algorithms for partial differential equations contain a great deal of parallelism. But this parallelism can be difficult to exploit, particularly on complex problems.One approach to extraction of this parallelism is the use of special purpose architectures tuned to a given problem class. The architecture proposed here is tuned to boundary value problems on complexdomains. An adaptive elliptic algorithm which maps effectively onto the proposed architecture is considered in detail.Two levels of parallelism are expol1ted by the proposed architecture.First, by making use of the freedom one has in grid generation, one can construct grids which are locally regular, permitting a one to one mapping of grids to systolic style processor arrays, at least over small regions. All local parallelism can be extracted by this approach. Second, though there may not be a regular global structure to the grids constructed, there will still be parallelism at this level. One approach to finding and exploiting this parallelism is to use an architecture having a number of processor clusters connected by a switching network. The use of such a network creates a highly flexible architecture which automatically configures to the problem being solved.

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Section: Architecturementioning

confidence: 99%

Parallel Architectures for Iterative Methods on Adaptive, Block Structured Grids

Gannon¹,

Vanrosendale²

1984

Elliptic Problem Solvers

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“…Because of this high cost, Multistage Interconnection Networks(MINs) have been proposed for interconnecting a large number of PEs. These MINS are candidates for variouson-going computer projects [15,17,24,31]. An NxN MIN basically employs logzN stages of 2x2 switcheswith N/2 number of such switches per stage.…”

Section: The Omega Networkmentioning

confidence: 99%

On the performance of loosely coupled multiprocessors

Bhuyan

1984

SIGARCH Comput. Archit. News

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A Processing Element (PE) essentially consists of a processor and a memory module. A loosely coupled multiprocessor is comprised of a set of such PEs interconnected through an Interconnection Network (IN).The designof the IN is crucial to an efficient communicationbeween the PEs.This paper presents approximate evaluations of two loosely coupled architectures, each having three types of INs, namely: shared bus, crossbar anda class of Multi stage Interconnection Networks (MINS) called Omega network. Probability of Acceptance (PA) of a message is considered as a measure of the performance.For a high rate of internal requests, it is shown that an Omega network performs close to a crossbar while reducing the the cost of interconnection to a large extent.

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“…In addition to PASM, ®ve other mixed-mode machines have been built: TRAC (University of Texas at Austin, USA) [14], OPSILA (University of Nice, France) [15], Triton (University of Karlsruhe, Germany) [16], EXECUTE (IBM, USA) [17], and MeshSP (ICE/MIT Lincoln Labs, USA) [18]. More information about mixedmode computing is in Ref.…”

Section: Introductionmentioning

confidence: 99%

Aspects of computational mode and data distribution for parallel range image segmentation

et al. 1999

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Parallel processing methods are a means to achieve signi®cant speedup of computationally expensive image understanding algorithms, such as those applied to range images. Practical implementations of these algorithms must deal with the problems of selecting an appropriate parallel architecture and mapping the algorithm onto that architecture. The parallel implementation approaches for range image segmentation that are presented here are applicable to many low-level image understanding algorithms in a variety of parallel architectures. An evaluation of initial data distribution is presented to determine whether a square subimage or a striped subimage distribution would result in the greatest overall reduction in execution time for the given range image segmentation problem. Novel implementations that consider each data distribution's treatment of edge pixels in window operations yield a trade-o between the number of data transfers versus the amount of computation. This trade-o is examined both analytically and experimentally. Additionally, using the same initial data distributions, a 0167-8191/99/$ ± see front matter Ó 1999 Published by Elsevier Science B.V. All rights reserved. PII: S 0 1 6 7 -8 1 9 1 ( 9 9 ) 0 0 0 0 7 -1 technique is introduced for changing the allocation of work to each of the processors to reduce the number of network settings by one half. This technique and the method for determining the better initial data distribution can be used with any machine and any window-based technique that requires a full window to perform image calculations. Comparisons of range image processing algorithms are performed using``pure'' SIMD algorithms,``pure'' MIMD algorithms, and mixed-mode implementations with both SIMD and MIMD elements. Each of these approaches are quantitatively analyzed and compared for implementing the dierent phases of a particular hybrid range segmentation algorithm. Results of this implementation study indicate that quanti®able reductions in execution time result from the proper choice of parallel mode for each portion of the segmentation process. Ó

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Organization of the TRAC processor-memory subsystem

Cited by 14 publications

References 5 publications

Parallel Architectures for Iterative Methods on Adaptive, Block Structured Grids

Parallel Architectures for Iterative Methods on Adaptive, Block Structured Grids

On the performance of loosely coupled multiprocessors

Aspects of computational mode and data distribution for parallel range image segmentation

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