ORCA: A new architecture for high-performance FPGAs

Hill, Dwight D.; Britton, B.K.; Oswald, William; Woo, Nam-Sung; Singh, Satwant; Chen, Che‐Tsung; Krambeck, Bob

doi:10.1007/3-540-57091-8_29

Cited by 8 publications

(4 citation statements)

References 5 publications

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“…Routing within a section would be simplified by keeping the system regular, supporting bus routing by enabling parallel signals to turn corners and retain their parallel organization (as was done in ORCA [14]) and in general, as discussed in Section 3, providing more than sufficient routing resources.…”

Section: Partitioned Fpgas For Speeding Up Compilationmentioning

confidence: 99%

Architectural and physical design challenges for one-million gate FPGAs and beyond

Rose

Hill

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current architectures will not extend directly to this scale because: they do not handle routing delays effectively; they require excessive compile/place/route times; and because they do not exploit new opportunities presented by the increase in available transistors and wiring. In this paper we describe several challenges that will need to be solved for these large-scale FPGAs to realize their full potential.

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Section: Partitioned Fpgas For Speeding Up Compilationmentioning

confidence: 99%

Architectural and physical design challenges for one-million gate FPGAs and beyond

Rose

Hill

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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“…The coarsegrain FPGA contains logic cells each of which has rich functionality, while the ne-grain FPGA contains logic cells with limited functionality. Coarse-grain FPGAs include AT&T's ORCA [1,2,3], Xilinx's XC4000 [4,5], Altera's Flex 8000 [6], and XC/ATT 3000 [7,8]. As an example, Figure 1 shows the combinational portion of a logic cell, called PLC (programmable logic cell), of the ORCA FPGA.…”

Section: Introductionmentioning

confidence: 99%

Revisiting the cascade circuit in logic cells of lookup table based FPGAs

Woo

1995

Proceedings of the 1995 ACM Third International Symposium on Field-Programmable Gate Arrays

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This paper shows that cascade circuits in the logic cells of all current lookup table based FPGAs support only linear cascading chain and, as a result, contribute to long cascading delay. W e present an enhanced cascade circuit that will reduce cascading delay signicantly: from linear time to log time in terms of the number of logic cells cascaded. We show that the additional area for the new cascade circuit is very small. We discuss an interaction between architecture design decision and CAD (in particular, placement) for the design of dedicated routing structure for cascade signals between logic cells. We illustrate the advantage of the new cascade circuit with an example of 32-bit equality c hecking circuit.

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“…The Xilinx XC4000 series [9] provides fast 2-bit addition at each logic cell by a special carry circuit. AT&T's ORCA [4] supports even 4-bit arithmetic operations. A 16 bit adder requires only four function blocks for example.…”

Section: Introductionmentioning

confidence: 99%

A new FPGA architecture for word-oriented datapaths

Hartenstein

Kress

Reinig

1994

Field-Programmable Logic Architectures, Synthesis and Applications

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Abstract.A new FPGA architecture (reconfigurable datapath architecture, rDPA) for word-oriented datapaths is presented, which has been developed to support a variety of Xputer architectures. In contrast to von Neumann machines an Xputer architecture strongly supports the concept of the "soft ALU" (reconfigurable ALU). Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The wordoriented datapath simplifies the mapping of applications onto the architecture. Pipelining is supported by the architecture. It is extendable to almost arbitrarily large arrays and is in-system dynamically reconfigurable. The programming environment allows automatic mapping of the operators from high level descriptions. The corresponding scheduling techniques for I/O operations are explained. The rDPA can be used as a reconfigurable ALU for bus-oriented host based systems as well as for rapid prototyping of high speed datapaths.

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ORCA: A new architecture for high-performance FPGAs

Cited by 8 publications

References 5 publications

Architectural and physical design challenges for one-million gate FPGAs and beyond

Architectural and physical design challenges for one-million gate FPGAs and beyond

Revisiting the cascade circuit in logic cells of lookup table based FPGAs

A new FPGA architecture for word-oriented datapaths

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