OR-Bridging Fault Identification and Diagnosis for Exclusive-OR Sum of Products Reed-Muller Canonical Circuits

Abstract

<b>Problem statement:</b> The faults in digital circuit can be classified broadly as single stuck-atfaults,&#13; multiple stuck-ay-faults, stuck-open faults, stuck-on faults, path delay faults, transient faults.&#13; Extensive research had been carried out in the field of testing of digital circuits to limit the number of&#13; input vectors. The cardinality of the test vectors proposed by many authors was quite high for large&#13; number of input variables. In this study a testable circuit with a small test set for detection and&#13; diagnosis of OR-bridging type fault in Reed-Muller canonical Exclusive-OR Sum of Products logic&#13; circuits, independent of the function for a given number of inputs had been proposed. <b>Approach:</b> A&#13; network structure comprising a set of Exclusive-OR gates and gates and a couple of auxiliary outputs&#13; were considered. The circuit as well as the test vectors were simulated by MATLAB coding. The faultfree&#13; and OR-bridging faults involving any two lines of control and data lines were then simulated. The&#13; outputs were represented in a compact decimal form for ease of tabulation. Two quantitative indices&#13; for comparison of results had also been discussed. Simulation and analysis for various random&#13; functions had been presented. <b>Results:</b> From the test results it was found that the identifiability for the&#13; set of random functions tested was more than 90% with just n + 5 test vectors compared to 2ⁿ test&#13; vectors required for conventional testing. It was also observed that even though the overall&#13; distinguishabililty factor was in the range of 45-80%, the individual set distinguishability was more&#13; than 90%. <b>Conclusion:</b> The proposed scheme had reduced the possibility of unidentifiable faults for&#13; the specified type of function. The location was also diagnosed through the output set. The analysis&#13; and diagnosis had been done through compact tabulation and two quantification indices

Power Optimization for Mixed Polarity Reed–Muller Circuits Based on Multilevel Adaptive Memetic Algorithm

“…end if (7) for all new list lines do (8) if the new list line is the same as the original list line then (9) Delete the new list line and the original list line (10) else (11) Add the new list line to the original list line (12) end if (13) end for (14) if r j �� 1, p j �� 2||r j �� 2, p j �� 1 then (15) Te…”

“…As shown in the aforementioned formulas, especially the (7), small F will afect the diference between individuals in the population and make the algorithm result fall into local optimal. Te F overlarge increase will enhance the global search ability of the algorithm but will afect the convergence speed of the algorithm and destroy the structure of the optimal solution.…”

“…where 0 end for (6) end for (7) while (|f(∆)| ≥ ε) or(t ≤ T) do (8) for i � 1 to M do (9) (Adaptive mutation and adaptive crossover) (10) for j � 1 to D do (11)…”

“…else if (exp (−de/T) > random (0, −1)) according to equations ( 14) and ( 15) then (6) f (∆ + i) � f (∆) (7) end if (8) T � λ * T ( 9) i++ (10) end while (11) return the New best vector ∆′ ALGORITHM 4: Te SAO algorithm.…”

“…With the emergence of XNOR and XOR gates, RM logic has attracted more and more attention. Circuits based on RM logic (such as arithmetic logic circuits and parity check circuits) show more obvious advantages in circuit power, area, and speed and have excellent testability [4][5][6][7]. Fixed polarity Reed-Muller (FPRM) expression and mixed polarity Reed--Muller (MPRM) expression are two common RM logic expansions [8].…”