OptMem: Dark-silicon aware low latency hybrid memory design

Abstract

Abstract-In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-transfer torque magnetic random-access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design.

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

“…Each cache level in the memory hierarchy has been designed with a different memory technology (Static Random Access Memory (SRAM), Embedded Dynamic Random Access Memory (eDRAM) and STT-RAM. Similarly, Onsori et al[101] proposed a hybrid memory system for DSCSs comprised of NVM devices. The propose architecture consists of STT-RAM memory banks which have been incorporated with SRAM memory banks.B.…”