Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits

Nabavi, Morteza; Ramezankhani, Farhad; Shams, M.

doi:10.1109/ted.2016.2517446

Cited by 19 publications

(14 citation statements)

References 18 publications

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“…Figure 7b shows the transient simulated waveform at 0.3 V (TT corner, 25 • C). Based on the sizing method in Reference [29], the proposed adder was sized through simulations in SMIC 130 nm technology. The transistor parameter settings of the proposed adder are shown in Table 1.…”

Section: Experiments Resultsmentioning

confidence: 99%

“…All the NMOS transistors used in this work were sized with the minimum channel width and length (W/L = 150 nm/130 nm) to utilize the reverse narrow channel effect to offer a relatively lower threshold voltage. Based on the sizing method in Reference [29], the proposed adder was sized through simulations in SMIC 130 nm technology. The transistor parameter settings of the proposed adder are shown in Table 1.…”

Section: Experiments Resultsmentioning

confidence: 99%

“…For comparison, a 16 bit modified CLA (MCLA) [15], a 16 bit adder based on asynchronous SAPTL (ADSA-SAPTL ADD) [24], a 16 bit SAPTL CLA [25], and a conventional 16 bit CLA [29] were also simulated using HSPICE in SMIC 130 nm technology. All these adders were sized based on the sizing scheme in Reference [29]. The V th of SMIC 130 nm technology ranges from 365 mV to 450 mV with the channel width changing when L = 130 nm.…”

Section: Comparison With Other Workmentioning

confidence: 99%

See 2 more Smart Citations

A Subthreshold Bootstrapped SAPTL-Based Adder Design

Zhang

Chen

2019

Electronics

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This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amplifier including a voltage boosting part and adopting an adder architecture based on bootstrapped SAPTL, significant improvements in performance and energy efficiency can be achieved. A case study of 16 bit adders in SMIC 130 nm technology demonstrated that the proposed adder outperformed other works in terms of performance, energy consumption, and energy efficiency. Furthermore, the statistical results of the Monte Carlo analysis proved the proposed adder’s significant enhancement of robustness against process and temperature variations. At 0.3 V (TT corner, 25 °C), the proposed 16 bit adder achieved improvements of 72% in performance and 8% in energy savings, as well as a 74% reduction in energy-delay production as compared with the current design.

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Section: Experiments Resultsmentioning

confidence: 99%

Section: Experiments Resultsmentioning

confidence: 99%

Section: Comparison With Other Workmentioning

confidence: 99%

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A Subthreshold Bootstrapped SAPTL-Based Adder Design

Zhang

Chen

2019

Electronics

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“…Standard CMOS-based resistive memory architectures consist of the association of a MOS transistor (usually a n-type MOS transistor to maximize the area density w.r.t to a p-type MOS [35] which must be at least two times bigger for the same…”

Section: Figurementioning

confidence: 99%

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

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With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.

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“…However the penalty of speed degradation is also obvious. One favorable method to obtain high speed subthreshold logic design is found by the maximum current overcapacitance ratio of a transistor [1].…”

Section: Introductionmentioning

confidence: 99%

Subthreshold Region based Linear Feedback Shift Register

Lakshmi,

Kamaraju,

Babulu

2019

IJEAT

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Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

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Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits

Cited by 19 publications

References 18 publications

A Subthreshold Bootstrapped SAPTL-Based Adder Design

A Subthreshold Bootstrapped SAPTL-Based Adder Design

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Subthreshold Region based Linear Feedback Shift Register

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