Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

Garrido, Mario; Paz, Pedro

doi:10.1109/tcsii.2020.3022528

Cited by 6 publications

(5 citation statements)

References 10 publications

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“…Finally, the last column is the total number of rotators, which is obtained by adding the numbers in columns two to five. In the table, previous architectures are sorted out by their radix, from radix-2 in the upper rows to radix-2 5 in the lower ones. The last row corresponds to the proposed architecture, which uses radix-2 4 .…”

Section: Comparison and Experimental Resultsmentioning

confidence: 99%

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A 5.2-GS/s 8-Parallel 1024-Point MDC FFT

Paz,

Garrido

2023

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)

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This paper presents an efficient 8-parallel 1024point multi-path delay commutator (MDC) fast Fourier transform (FFT) implementation on a field-programmable gate array (FPGA). The selection of the FFT algorithm and the data orders allow for obtaining an architecture with 23 non-trivial rotators, which is the minimum number achieved so far. Additionally, the non-general rotators in the architecture are trivial rotators, constant rotators, and 1-rots, which require very few resources to be implemented. The deep pipelining in the architecture allows for reaching a throughput of 5.2 GS/s.Index Terms-Fast Fourier transform (FFT), multi-path delay commutator (MDC), pipelined architecture.

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Section: Comparison and Experimental Resultsmentioning

confidence: 99%

“…100%. Likewise, it is possible to obtain optimum MDC architectures in terms of the total memory used in the permutation circuits [5]. However, for small and medium-sized MDC FFTs, rotators are usually the most expensive elements in terms of resources.…”

Section: Introductionmentioning

confidence: 99%

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT

Paz,

Garrido

2023

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)

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“…input, output, and through the FFT. In fact, the number of alternatives is large, as happens for MDC FFTs [45].…”

Section: Proposed Msc Fft Architecturesmentioning

confidence: 99%

Radix-2^k MSC FFT Architectures

et al. 2023

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In recent years, the SC FFT architecture has become popular for processing serial data. It requires a small number of components and achieves full utilization of the butterflies, which improves previous serial FFT architectures. By contrast, the MSC FFT architecture, which is the parallel version of the SC FFT, has not been studied in depth in the literature and it has not been analyzed if this new type of FFT architecture improves previous parallel FFTs. The aim of this paper is to provide a rigorous study of MSC architectures that expands the field of FFT architectures by incorporating fundamental knowledge about this promising FFT. With this goal, this paper proposes new MSC FFT architectures for any FFT size, radix, and parallelization. In order to derive these architectures, efficient modules have been developed. These modules are connected by permutation circuits to create the architectures. The optimization of the modules results in a reduction in the number of rotators and their complexity compared to previous designs. As a result, the proposed architectures not only achieve high throughput due to their parallel nature but also the lowest hardware complexity among parallel pipelined FFT architectures so far. To verify the architectures and compare the proposed approach to previous works, a 1024-point MSC FFT architecture has been implemented. Experimental results show that the architecture achieves a throughput of 1.32 gigasamples per second, and reduces the area and power consumption significantly with respect to previous designs.INDEX TERMS Fast Fourier transform (FFT), multi-path serial-commutator (MSC), pipelined architecture, radix-2 k .

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“…The rotator complexity in MDC FFT architectures can be reduced even more by using higher radices, such as radix-2 3 or 2 4 [33] and by exploring other data orders that allocate the rotators in only some of the parallel branches [34,38].…”

Section: The MDC Fft Architecturementioning

confidence: 99%

“…However, the amount and complexity of rotators in FFT architectures still need to be optimized. As a result, recent FFT architectures [34,37,38] focus on reducing the number of rotators and their complexity, which requires to study different data orders and obtain the best results among them in terms of rotators.…”

Section: Rotations In Fft Architecturesmentioning

confidence: 99%

A Survey on Pipelined FFT Hardware Architectures

Garrido

2021

J Sign Process Syst

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The field of pipelined FFT hardware architectures has been studied during the last 50 years. This paper is a survey that includes the main advances in the field related to architectures for complex input data and power-of-two FFT sizes. Furthermore, the paper is intended to be educational, so that the reader can learn how the architectures work. Finally, the paper divides the architectures into serial and parallel. This classification puts together those architectures that are conceived for a similar purpose and, therefore, are comparable.

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Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

Cited by 6 publications

References 10 publications

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT

Radix-2^k MSC FFT Architectures

A Survey on Pipelined FFT Hardware Architectures

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Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers

Cited by 6 publications

References 10 publications

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT

Radix-2 k MSC FFT Architectures

A Survey on Pipelined FFT Hardware Architectures

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Radix-2^k MSC FFT Architectures