Optimizing two-phase, level-clocked circuitry

Ishii, Alexander T.; Leiserson, Charles E.; Papaefthymiou, Marios C.

doi:10.1145/256292.256301

Cited by 76 publications

(55 citation statements)

References 14 publications

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“…We generally order the phases such that e i < e j if i < j and choose e n as the global time reference. In particular, if e i = (i/n)T , the clock schedule is symmetric [10]. The setup and hold times are denoted as X i and H i , respectively.…”

Section: Clock Modelmentioning

confidence: 99%

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk

Lin

Zhou²

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Latches are extensively used in high-performance sequential circuit designs to achieve high frequencies because of their good performance and time-borrowing feature. However, the amount of timing uncertainty due to crosstalk accumulated through latches could be larger than the benefit gained by time borrowing. In this paper, we show that the tradeoff between a latch and a flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of mixed latches and flops. A circular time representation is proposed to make coupling detection easier and more efficient. Experiments on our heuristic algorithm for finding an optimal configuration of mixed latches and flops showed promising results.

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Section: Clock Modelmentioning

confidence: 99%

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk

Lin

Zhou²

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Sakallah, Mudge, and Olukoton developed the SMO model [16] which was widely adopted within the timing verification and optimization community. Ishii, Leiserson, and Papaefthymiou also provide a general framework for the timing verification of 2-phase level-clocked circuits [11]. Schedule verification algorithms were based on one of two approaches.…”

Section: B Verifying Clock Schedulesmentioning

confidence: 99%

“…Lockyear's approach [14] and Ishii et. al's approach [11], however, are based on determining the amount of time in which a computation must complete. This approach also results in efficient polynomial algorithms for verifying schedules.…”

Section: B Verifying Clock Schedulesmentioning

confidence: 99%

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Static timing analysis for level-clocked circuits in the presence of crosstalk

Hassoun

Cromer²,

Calvillo-Gamez³

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Static timing analysis is instrumental in efficiently verifying a design's temporal behavior to ensure correct functionality at the required frequency. This paper addresses static timing analysis in the presence of cross talk for circuits containing levelsensitive latches, typical in high-performance designs. The paper focuses on two problems. First, coupling in a sequential circuit can occur because of the proximity of a victim's switching input to any periodic occurrence of the aggressor's input switching window. This paper shows that only three consecutive periodic occurrences of the aggressor's input switching window must be considered. Second, an arrival time in a sequential circuit is typically computed relative to a specific clock phase. The paper proposes a new phase shift operator to align the aggressor's three relevant switching windows with the victim's input signals. This paper solves the static analysis problem for level-clocked circuits iteratively in polynomial time, and it shows an upper bound on the number of iterations equal to the number of capacitors in the circuit. The contributions of this paper hold for any discrete overlapping coupling model. The experimental results demonstrate that eliminating false coupling allows finding a smaller clock period at which a circuit will run.

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“…Leiserson and Saxe developed algorithms both for cycle time minimization and for register area minimization of circuits with edge triggered flip flops. Since then, many improvements and extensions to the original ideas have been developed, like acceleration techniques [3], which dramatically speed up execution time, algorithms for retiming level clocked circuits [4] [5], algorithms taking registers setup and hold times into account [6] [7], algorithms for retiming registers with enable inputs [8] as well as algorithms that can improve testability [9].…”

Section: Introductionmentioning

confidence: 99%

Tight coupling of timing-driven placement and retiming

Neumann¹,

Kunz²

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

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Retiming is a widely investigated technique for performance optimization. In general, it performs extensive modifications on a circuit netlist, leaving it unclear, whether the achieved performance improvement will still be valid after placement has been performed. This paper presents an approach for integrating retiming into a timing-driven placement environment. The experimental results show the benefit of the proposed approach on circuit performance in comparison with design flows using retiming only as a pre-or postplacement optimization method.

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Optimizing two-phase, level-clocked circuitry

Cited by 76 publications

References 14 publications

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk

Static timing analysis for level-clocked circuits in the presence of crosstalk

Tight coupling of timing-driven placement and retiming

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