Optimizing the memory bandwidth with loop fusion

Marchal, Paul Alfred; Gómez, José Ignacio Aguaded; Catthoor, Francky

doi:10.1145/1016720.1016767

Cited by 24 publications

(18 citation statements)

References 22 publications

(27 reference statements)

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“…The main works in this area include loop fusion [9,13] and reversal [10]. Loop fusion enhances both temporal and spatial locality and is best used when the two loop bodies to be fused share the same array(s).…”

Section: Combination With Fusion and Reversalmentioning

confidence: 99%

“…Loop fusion is applied recursively in order to allow more than two loops to be combined. Other details regarding the application of loop fusion and loop reversal are omitted due to the lack of space and can be found in [9,13,12].…”

Section: Optimization Algorithmmentioning

confidence: 99%

“…Optimizing multiple loop nests at a time requires more advanced analysis and informative representations of the program. Traditional techniques such as loop fusion [9,13] and reversal [10] have been used in this area but their benefits are diminishing because of increasing program complexity. Global fusion algorithms also have some limitations.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering

Naci

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Section: Combination With Fusion and Reversalmentioning

confidence: 99%

Section: Optimization Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering

Naci

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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“…In [46], we present a heuristic to decide which loops to combine. The input of the algorithm is an initial description of the loops, their statements and iteration domains.…”

Section: Global Schedule: Loop Morphingmentioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain. The design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [53]. These systems require an enormous computational performance (40GOPS 1 ). Even though current PCs offer this performance requirement, they consume too much power (10-100W). Mobile devices should consume at least two or three orders of magnitude less power [30]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. The era of platform-based designA platform is a fixed micro-architecture together with a programming environment that minimizes mask-making costs and is flexible enough to work for a set of applications [4]. The production volumes can then remain high over an extended chip lifetime.Given the strong energy constraints, we must choose the flavor of these platforms. Since power is cubic to the processing frequency, parallelism is an effective to reduce power and energy consumption. Then, multiple simple processors are preferred to one complex speculative and out-of-order processor. In the right application domain, we can get better performance and spend less energy. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a Digital Signal Processor (DSP). The RISC is more energy-efficient for the input/output processing and simple control-dominated 1 Giga Operations Per Second

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“…Therefore, we have presented a decision mechanism in [72]. It pairwise fuses loops, which considers memory size, number of ports, access latency and assignment constraints.…”

Section: Loop Morphingmentioning

confidence: 99%

Power aware data and memory management for dynamic applications

Marchal

Perez

Atienza

et al. 2005

IEE Proc., Comput. Digit. Tech.

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multiprocessor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads into account and do not deal with the dynamic behaviour of these novel applications. The main limitations of current techniques are outlined and an approach for dealing with them is introduced. Design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [1]. These systems require an enormous computational performance: 40 gigaoperations per second (GOPS). Even though current PCs could provide sufficient performance, they are too powerhungry (10 -100 W). Mobile devices should consume at least two or three orders of magnitude less [2]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently, and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. Era of platform-based designA platform is a fixed microarchitecture together with a programming environment that minimises mask-making costs and is flexible enough to work for a set of applications [3]. The production volumes can then remain high over an extended chip lifetime.To cope with the energy constraints, platforms usually consist of multiple processors. Since power is cubic to the processing frequency, parallelism is an effective way to reduce it. Therefore, on most platforms two or more processors are integrated. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a digital signal processor (DSP). The RISC is more energy-efficient for the input=output processing and control-dominated applications. The DSP, however, provides the computational performance for audio and video processing, while keeping the energy cost bounded. Indeed, taking a look to the current market offers (e.g. ST Nomadik

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Optimizing the memory bandwidth with loop fusion

Cited by 24 publications

References 22 publications

Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering

Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering

Power-efficient data management for dynamic applications

Power aware data and memory management for dynamic applications

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