Proceedings of Technical Program of 2012 VLSI Technology, System and Application 2012
DOI: 10.1109/vlsi-tsa.2012.6210167
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Optimizing state-of-the-art 28nm core/SRAM device performance by cryo-implantation technology

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Cited by 6 publications
(2 citation statements)
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“…Positive results are reported such as 3.5% device gain, junction leakage reduction, and DIBL improvement [1]. In this paper, Ga replacing single HS-P halo studies were conducted for SRAM or core NFET devices using a similar 28nm poly-SiON process reported previously [2][3][4].…”
Section: Introductionmentioning
confidence: 86%
See 1 more Smart Citation
“…Positive results are reported such as 3.5% device gain, junction leakage reduction, and DIBL improvement [1]. In this paper, Ga replacing single HS-P halo studies were conducted for SRAM or core NFET devices using a similar 28nm poly-SiON process reported previously [2][3][4].…”
Section: Introductionmentioning
confidence: 86%
“…The single step HS-P cluster halo was replaced with Ga with energy and dose splits. Figure 2 Process flow for halo studies with Ga replacing 50% or up to 100% HS-P halo using a 28nm Poly-SiON process [2][3][4]. Bare wafers were generated for as-implant and post annealed 1 D profiles with these process steps as shown in box.…”
Section: Methodsmentioning
confidence: 99%