Optimizing software data prefetches with rotating registers

Abstract

Software data prefetching is a well-known

Optimization to Prevent Cache Penalty by Loop Partition and Loop Unrolling

“…出现代价的两条存取指令必须具备一定的条件,可将这些条件分为 cache 条件和调度条件.cache 条件主要 表现为两条存取指令访问存储系统的相同单元以及是否命中 cache 等,硬件单元的大小称为代价长度(penalty size,简称 S P ).表 1 列出了 Itanium 2 的所有代价类型以及相应的代价长度、cache 条件. 大多数处理机都支持数据预取技术,与图 1(d)相比,图 1(e)需要添加数据预取指令,这可能会导致执行更多的冗 余预取指令,但利用条件执行或旋转寄存器能够避免执行冗余的预取指令 [17] .此外,旋转寄存器还能够避免添加 多余的预取指令. 赖.分割可分循环所得的子循环的数目被称为分割展开因子(partition-unrolling factor,简称 F PU ).…”

Impact of Compiler-based Data-Prefetching Techniques on SPEC OMP Application Performance

“…The Intel Itanium 2 architecture also provides support for memory access hints that enable compilers to orchestrate data movement between memory hierarchies efficiently [5]. For example, if a data reference does not exhibit any kind of reuse, then it can be prefetched using a special lfetch 'nta' hint to reduce cache pollution.…”

“…There are a number of techniques that have been intensively studied to address this performance issue. These techniques fall into two categories: latency tolerance and latency elimination [5,11,13].…”

“…Software data-prefetching is an effective latency tolerance technique that is aimed at hiding the memory access latency by overlapping it with time to compute results and time to access other memory locations [5,11,13]. The long latency elimination techniques, also called locality optimizations, are aimed at minimizing long memory latency [13] through maximizing data and instruction reuse at cache levels of the memory hierarchy.…”

“…The software data-prefetching framework implemented in the Intel® Itanium® compiler [5,10] provides the required infrastructure for our performance study. Most of the compiler analyses and optimizations that are needed to enable effective software data-prefetching are done before data-prefetching utilizing the services of an advanced memory disambiguation module.…”