Optimizing pipeline for a RISC processor with multimedia extension ISA

Xiao, Zhibin; Liu, Peng; Yao, Yingbiao; Yao, Qingdong

doi:10.1631/jzus.2006.a0269

Cited by 11 publications

(4 citation statements)

References 10 publications

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“…The experimental platform integrates one 32-bit integer RISC core -RISC32E [10] and eight 32-bit integer DSPs -MediaDSP3200 [11][12]. A 3x3 mesh topology NoC connects them and the DMA engine is also included.…”

Section: Evaluation Methodologymentioning

confidence: 99%

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

Yang

Wu³

et al. 2011

Lecture Notes in Computer Science

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Abstract. How to manage the message passing among inter processor cores with lower overhead is a great challenge when the multi-core system is the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. Generally speaking, the networks-on-chip connects the distributed multi-core system. It takes charge of message passing which including data and synchronization message among cores. The size of most data transmission is typically large enough that it remains strongly bandwidth-bound. The synchronization message is very small which is primarily latency bound. Thus the separated networks-on-chip are needed to transmit the above two types of message. In this paper we focus on the network for the transmission of synchronization messages. A hardware module -message passing unit (MPU) is proposed to manage the synchronization message passing for the heterogeneous multi-core system. Compared with the original single network approach, this solution reduces the run-time object scheduling and synchronization overhead effectively, thereby, improving the whole system performance.

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Section: Evaluation Methodologymentioning

confidence: 99%

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

Yang

Wu³

et al. 2011

Lecture Notes in Computer Science

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“…Table 1 shows the struts specifications and Table 2 shows the distribution of the initial prestress which could be obtained by the balance matrix theory and the dynamic relaxation method [2] . The value of initial prestress of structure is balanced with the weight of upper rigid reticulated shell and the full-span load 0.6KN/m 2 , and in this paper, the vibration characteristics of BSS are analyzed through finite element program-ANSYS [3] .…”

Section: Structural Arrangementmentioning

confidence: 99%

“…For this new latticed shell string structure, a 1/15 scale model of the roof of Yueqing Municipal Gymnasium was constructed in the document [2] and the experiment included simulation of tension process and static loading. Based on the local analysis method and the nodal equilibrium equation, the simplified calculation method and the improved numerical algorithm were put forward in the document [3].In this paper, the vibration characteristics of this new latticed shell string structure was analyzed, which provide a research foundation for the analysis of seismic and wind effect [4].…”

Section: Introductionmentioning

confidence: 99%

Study on Dynamic Characteristics of a New Space Latticed Shell String Structure

Yao

Dong

2014

AMR

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Latticed shell string structure with inner and outer truss torus, radial cables of which emerge from the roof, is proposed. Ribbed latticed shell string structure with a span of 100m is taken as an example and the modal analysis is performed. The effects of the rises of radial cables and the curvatures of latticed shell on dynamic characteristics of this structure are also investigated. The result reveals some characteristics of modal of the latticed shell string structure with inner and outer truss torus, which could be referenced by structure designers.

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“…We have developed the soft reduced instruction set computer (RISC) IP core (Xiao et al, 2006) that is compatible with MIPS 32 instruction set architecture (http://www.mips.com). The RISC core is linked with the emulated NoC through the NI.…”

Section: Hardware Layermentioning

confidence: 99%

A networks-on-chip emulation/verification framework

Liu

Xia

et al. 2011

IJHPSA

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The emulation and functional validation are essential to the assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection network architectures. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy and decrease the usage of the resources of field programmable gate array.

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Optimizing pipeline for a RISC processor with multimedia extension ISA

Cited by 11 publications

References 10 publications

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System

Study on Dynamic Characteristics of a New Space Latticed Shell String Structure

A networks-on-chip emulation/verification framework

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