Optimizing matrix transposes using a POWER7 cache model and explicit prefetching

Abstract

We consider the problem of efficiently computing matrix transposes on the POWER7 architecture. We develop a matrix transpose algorithm that uses cache blocking, cache prefetching and data alignment. We model the POWER7 data cache and memory concurrency and use the model to predict the memory throughput of the proposed matrix transpose algorithm. The performance of our matrix transpose algorithm is up to five times higher than that of the dgetmo routine of the Engineering and Scientific Subroutine Library and is 2.5 times higher than that of the code generated by compiler-inserted prefetching. Numerical experiments indicate a good agreement between the predicted and the measured memory throughput.

Optimizing matrix transposes using a POWER7 cache model and explicit prefetching

“…Based on the model, we have designed a matrix transpose code whose memory bandwidth is higher than that of the dgetmo routine. The full paper can be found in [2].…”

HPTT: a high-performance tensor transposition C++ library

“…Two-dimensional tensor transposition (i.e., matrix transposition) is a well studied operation, including optimizations for blocking, vectorization, unrolling, and software prefetching [3,6,11,13,14,25]. The same optimizations are investigated in the context threedimensional out-of-place tensor transpositions on CPUs [10,22].…”

TTC: a tensor transposition compiler for multiple architectures

“…10 To assess the performance of TTC across a wide range of use cases, we report TTC's bandwidth on a synthetic tensor transpositions benchmark [14]. 11 The benchmark comprises a total of 57 transpositions ranging from 2D to 6D; each tensor of the benchmark is of size 200 MB.…”

“…10 Linux applies the first touch policy, meaning that data is allocated close to the thread which touches the data first-not the thread who allocates the data. 11 The complete benchmark is available at www.github.com/HPAC/TTC/tree/master/benchmark formance for HSW ( Fig. 5b) and M840 (Fig.…”

“…Due to the non-contiguous memory access patterns and the vast number of architecture-specific optimizations required by modern vector processors (e.g., vectorization, blocking for caches, nonuniform memory accesses (NUMA)), writing high-performance tensor transpositions is a challenging task. Until now, many research efforts focused on 2D [5,9,11,12,18] and 3D transpositions [8,15], while higher dimensional transpositions [10,19] are mostly still uncovered.…”