Optimizing logic design using Boolean transforms

Chavda, P.; Jacob, J.; Agrawal, Vishwani D.

doi:10.1109/icvd.1998.646605

Cited by 2 publications

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“…By an argument similar to the above, faults on these are detected at z by T(C2). 3. Checkpoints x1, x2, .…”

Section: Suppose We Apply the Combined Test Set T(c1)+t(c2)mentioning

confidence: 99%

Choice of tests for logic verification and equivalence checking and the use of fault simulation

Agrawal¹

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design

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A new method is proposed for checking the equivalence of two irredundant logic implementations of a combinational Boolean function. The procedure consists of generation of complete checkpoint fault test sets for both circuits. The two test sets are concatenated and both circuits are simulated to obtain the response to the combined test set. If the responses of the two circuits match for all vectors, then they are declared to be e quivalent. We examine a case where this heuristic fails. In such cases, the use of fault simulation is shown to discover nonequivalence even when the two circuits produce the same output. We prove that if the two circuits were di erent, then some faults on the primary inputs of a composite equivalence checking circuit must be detectable. Using the simulation of single stuck-at faults at the primary inputs of that circuit, the new heuristic recommends the use of a vector set in which the Hamming distance between any two vectors does not exceed 3 .

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“…By an argument similar to the above, faults on these are detected at z by T(C2). 3. Checkpoints x1, x2, .…”

Section: Suppose We Apply the Combined Test Set T(c1)+t(c2)mentioning

confidence: 99%