Optimized surface code communication in superconducting quantum computers

Abstract

Quantum computing (QC) is at the cusp of a revolution. Machines with 100 quantum bits (qubits) are anticipated to be operational by 2020 [30,73], and several-hundred-qubit machines are around the corner. Machines of this scale have the capacity to demonstrate quantum supremacy, the tipping point where QC is faster than the fastest classical alternative for a particular problem. Because error correction techniques will be central to QC and will be the most expensive component of quantum computation, choosing the lowest-overhead error correction scheme is critical to overall QC success. This paper evaluates two established quantum error correction codes-planar and double-defect surface codes-using a set of compilation, scheduling and network simulation tools. In considering scalable methods for optimizing both codes, we do so in the context of a full microarchitectural and compiler analysis. Contrary to previous predictions, we find that the simpler planar codes are sometimes more favorable for implementation on superconducting quantum computers, especially under conditions of high communication congestion.

Asymptotic improvements to quantum circuits via qutrits

“…Given the severe constraints on quantum resources, it is critical to fully optimize the compilation of a quantum algorithm in order to have successful computation. Prior architectural research has explored techniques such as mapping, scheduling, and parallelism [6][7][8] to extend the amount of useful computation possible. In this work, we consider another technique: quantum trits (qutrits).…”

Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers

“…First, we place frequently interacting qubits near each other by bisecting the qubit interaction graph along a cut with few crossing edges, computed by the METIS graph partitioning library [26]. As described in previous work [13,19], this strategy is applied recursively on the partitions, yielding a heuristic mapping that reduces the distances of CNOT operations.…”

Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures

“…Surface code braid scheduling costs were analyzed in [1] using an end-to-end toolflow. The work focused on the resource impact of the choice of different implementation styles of surface code logical qubits.…”

“…We present the first detailed designs of hardware functional units that implement space-time optimized magic-state factories for surface code error-corrected machines.Interactions among distant qubits require surface code braids (physical pathways on chip) which must be routed. Magic-state factories are circuits comprised of a complex set of braids that is more difficult to route than quantum circuits considered in previous work [1]. This paper explores the impact of scheduling techniques, such as gate reordering and qubit renaming, and we propose two novel mapping techniques: braid repulsion and dipole moment braid rotation.…”