Optimized implementation of OpenCL kernels on FPGAs

Shata, Kholoud; Elteir, Marwa K.; El-Zoghabi, Adel A.

doi:10.1016/j.sysarc.2019.02.013

Cited by 18 publications

(11 citation statements)

References 6 publications

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“…In the OpenCL execution architecture, the host-side program is used to uniformly manage and schedule multiple computing devices that support OpenCL [31]. When the host side submits the kernel to the computing device, OpenCL defines the organizational structure of the work-item through the index space and defines how the kernel operates on the computing device in a mapping manner on the computing device [32], [33]. In the OpenCL abstract model, each instance of the execution kernel is called a work-item, which is represented by its coordinates in the NDRange.…”

Section: A Opencl Parallel Computing Platformmentioning

confidence: 99%

A Parallel Algorithm of Image Mean Filtering Based on OpenCL

et al. 2021

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The image will be contaminated by noise during the imaging process, which severely degrades the image quality. It is necessary to filter the collected image. With the increasing amount of image data, the traditional single-processor or multiprocessor computing equipment has been unable to meet the requirements of real-time data processing. In this paper, the computational model of weighted mean filtering and the characteristics of high performance computer architecture are studied. An efficient hierarchical image weighted mean filtering parallel algorithm for Open Computing Language (OpenCL) is designed and implemented, which can fully express the parallelism of the computing model. The parallel algorithm takes full account of the characteristics of image discrete convolution computing and the multilayer logic architecture of high performance computer, deeply excavates the parallelism of the computing platform and computing model, and realizes the efficient task mapping from computing model to computing resources. The model is implemented in parallel with the two levels of work-group and workitem. The experimental results show that compared with the serial algorithm based on CPU, the parallel algorithm based on Open Multi-Processing (OpenMP) and the parallel algorithm based on Compute Unified Device Architecture (CUDA), the parallel algorithm of weighted mean filtering achieves 20.88 times, 18.52 times and 1.26 times acceleration ratio on the NVIDIA GPU computing platform based on OpenCL architecture, respectively. It realizes better computing performance and runs on different Graphic Processing Unit (GPU) computing platforms, and has good portability and scalability.INDEX TERMS weighted mean filtering; Gaussian noise; Graphic Processing Unit (GPU); Open Computing Language (OpenCL); parallel algorithm.

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Section: A Opencl Parallel Computing Platformmentioning

confidence: 99%

A Parallel Algorithm of Image Mean Filtering Based on OpenCL

et al. 2021

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“…Nowadays, the Matlab based high level coding is advantageous for user prospective [19]. But the Matlab converted verilog/VHDL code is generalized in nature and is not optimal [21]. Such implementation uses more resources and introduces computational complexities as compare to the same algorithm implemented with low level Verilog/VHDL coding.…”

Section: Proposed Hardwarementioning

confidence: 99%

“…Recently, the FPGA vendors presented an open computing language (OpenCL) [20] to get two-fold benefits: (i) A generalized coding environment for different vendors' FPGAs, and (ii) Abstract (high-level) coding environment for an FPGA. Although the programming of an FPGA by this high level language/software significantly reduces the development time compared to the traditional lowlevel languages (e.g., Verilog or VHDL) but results in significantly under-utilizing the computing capabilities of the device [21]. Thus, a trade-off exist between ease of coding and optimized coding.…”

Section: Introductionmentioning

confidence: 99%

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FPGA Implementation of RLSE Algorithm for Multichannel Brain Imaging

Nazir

Khan

Akram

et al. 2021

Mehran Univ. res. j. eng. technol.

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This paper describes the implementation of a computationally efficient embedded system on an Field Programmable Gate Array (FPGA) platform for real-time brain activity estimation with multiple channels. The brain signals from multiple channels are considered as output of independent linear systems with unknown parameters representing the brain activity in corresponding channels. Multiple adaptive Recursive Least-Squares Estimation (RLSE) cores are implemented in FPGA to independently estimate the brain activity in each channel concurrently. The proposed RLSE-FPGA system provides dedicated (no time or resource sharing) and parallel processing environment. The universal asynchronous receiver transmitter core is also developed to communicate the measured and estimated parameters supported by storage facility programmed as shared memory. The computational precision is guaranteed by deploying a 32-bit floating point core for all the variables. The validation carried out by real Functional Near-Infrared Spectroscopy dataset and comparative analysis with the previously reported result, demonstrates the effectiveness of the proposed system. The computational cost endorses the effectiveness of concurrent processing of multiple channelsꞌ data in a sample before the arrival of the next sample. The proposed methodology has potential in real-time medical, military and industrial applications.

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“…Shata et al present a lengthy study of several generic code optimizations for OpenCL kernels [33]. These include avoiding the use of global variables (e.g., for reduce operations), studying the effect of suggested or enforced work-group size for different kernels, and employing inter-kernel channels.…”

Section: Related Workmentioning

confidence: 99%

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

2020

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High Level Synthesis (HLS) tools targeting Field Programmable Gate Arrays (FPGAs) aim to provide a method for programming these devices via high-level abstractions. Initially, HLS support for FPGAs focused on compiling C/C++ to hardware circuits. This raised the issue of determining the programming practices which resulted in the best performing circuits. Recently, to further increase the applicability of HLS approaches, renewed effort was placed on support for HLS of OpenCL code for FPGA, raising the same issues of coding practices and performance portability. This paper explores the performance of OpenCL code compiled for FPGAs for different coding techniques. We evaluate the use of task-kernels versus NDRange kernels, data vectorization, the use of on-chip local memories, and data transfer optimizations by exploiting burst access inference. We present this exploration via a case study of the k-means algorithm, and produce a total of 10 OpenCL implementations of the kernel. To determine the effects of different data set characteristics, and to determine the gains from specialization based on number of attributes, we generated a total of 12 integer data sets. The data sets vary regarding the number of instances, number of attributes (i.e., features), and number of clusters. We also vary the number of processing cores, and present the resulting required resources and operating frequencies. Finally, we execute the same OpenCL code on a 4 GHz Intel i7-6700K CPU, showing that the FPGA achieves speedups up to 1.54× for four cases, and energy savings up to 80 % in all cases.

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Optimized implementation of OpenCL kernels on FPGAs

Cited by 18 publications

References 6 publications

A Parallel Algorithm of Image Mean Filtering Based on OpenCL

A Parallel Algorithm of Image Mean Filtering Based on OpenCL

FPGA Implementation of RLSE Algorithm for Multichannel Brain Imaging

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

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