Optimized design of a digital I/Q demodulator suitable for adaptive pre-distortion of 3rd generation base station PAs

Abstract

This article presents an optimized design of a high-speed digital I/Q demodulator intended for the implementation of the feedback path of an adaptive base band digital pre-distorter (DPD). Indeed, the optimization of the DPD linearization capability, in terms of correction bandwidth and nonlinearity effects minimization, is directly related to the accuracy and speed of the I/Q demodulator. In this work, a digital I/Q demodulator is designed, optimized and implemented in a Xilinx FPGA device. This allowed for high-speed processing of about 200 MHz with a substantial reduction in the FPGA used gates.