Optimized cobalt silicide formation through etch process improvements

Abstract

Cobalt silicide is used to reduce contact resistance for sub-micron technology such as 0.25um CMOS. At National Semiconductor, a thin oxide is used to protect areas that are not to be silicided. The selective removal of this oxide to form the silicide mask is critical as it occurs in the highly sensitive cobalt silicide module where neither over nor under etch is acceptable. The final etch uses a low power, CHF 3 /Ar recipe with good across wafer uniformity. In keeping with the advanced process control methodology at National, the etch is end pointed to reduce wafer-to-wafer and etch chamber variability. This paper contains integration aspects of the cobalt silicide module as well as the specifics of the new etch process. The effects of power, pressure and gas flows and details of the end point set up are reviewed, as well as cross section analysis and electrical responses.