Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area

A Review of Charge Pump Topologies for the Power Management of IoT Nodes

“…A technique allowing for the reduction of rise time or silicon area occupation, thanks to the reduction on the number of stages and using a clock boosted topology, is presented in [54,55]. These CPs use clock signals with amplitudes higher than the supply voltage, thus requiring additional blocks (other charge pumps) to boost the preexisted clock.…”

“…A qualitative analysis of this structure highlights that, although a reduction of stages can be obtained, the rushing fall in the driving capability, due to cascade configuration, constrains to an increase of the total capacitance values of the whole pump, nullifying the proposal's benefits. Recently, the authors in [55] adopted the clock booster to reduce the rise time or area occupation in CPs, with a clock amplitude doubled with respect to supply voltage, proving proper sizing strategies. In general, despite the achieved benefits, this approach is not suitable for low-power and/or energy efficient application.…”

“…In conclusion, this approach allows about 9.95% of power consumption reduction, with only 1-2% of area penalty. Recently, the authors in [55] adopted the clock booster to reduce the rise time or area occupation in CPs, with a clock amplitude doubled with respect to supply voltage, proving proper sizing strategies. In general, despite the achieved benefits, this approach is not suitable for low-power and/or energy efficient application.…”

Linear distribution of capacitance in Dickson charge pumps to reduce rise time

“…In nonvolatile memory applications, such as NOR Flash memories, where the word line (WL) has a capacitance in the order of 10 pF, or recent 3D NAND, where capacitance is 2× and 4× higher for a selected WL and deselected WLs, respectively, rise time and (or) silicon area minimization of the CP are the main design targets . In particular, WLs of recent 3D NAND have to be biased to about 6 to 8 V for read and to 10 to 20 V for program .…”

“…A generalized and simplified Dickson CP block diagram is depicted in Figure 1, where the block named charge transfer switch (CTS) 6 has the function of irreversibly transferring charge from the input to the output and works like a diode (as in the first Dickson CP) or a switch.In nonvolatile memory applications, such as NOR Flash memories, 7 where the word line (WL) has a capacitance in the order of 10 pF, or recent 3D NAND, 8 where capacitance is 2× and 4× higher for a selected WL and deselected WLs, respectively, rise time and (or) silicon area minimization of the CP are the main design targets. [9][10][11] In particular, WLs of recent 3D NAND have to be biased to about 6 to 8 V for read and to 10 to 20 V for program. 8 As WL capacitance increases, the CP area would have to increase to keep the WL rise time unchanged, which would result in larger silicon area and higher power.…”