Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT‐Based Image Compression

Jridi, Maher; Alfalou, Ayman; Meher, Pramod Kumar

doi:10.1155/2012/209208

Cited by 12 publications

(8 citation statements)

References 40 publications

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“…Hsu and Cheng in [ 32 ] investigated prediction algorithm to reduce the resource usage of the DCT architecture. In [ 33 ], the authors claimed least hardware resource usage with efficient power consumption. Their architecture is based on joint optimization of CSD, CSE, and quantization.…”

Section: Methodsmentioning

confidence: 99%

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Siddiqui

Reza

Kanesan

et al. 2014

The Scientific World Journal

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A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

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Section: Methodsmentioning

confidence: 99%

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Siddiqui

Reza

Kanesan

et al. 2014

The Scientific World Journal

View full text Add to dashboard Cite

show abstract

“…Thus, Config4 allowed a power efficiency about 7.7 times better than what we could obtain with Config1. We finally should note that hardware performance may be enhanced when using predictive computation techniques as in [33] to predict zero quantized DCT coefficients, or also by a fine hardware optimization of arithmetic operations used in the DCT, as in [34].…”

Section: Resource Utilizationmentioning

confidence: 99%

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

Jridi

Chapel

Dorez

et al. 2018

JLPEA

Self Cite

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This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times.

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“…Sun and Yang [2] proposed an image compression method based on a Laplace transparent composite model to achieve high coding efficiency. Jridi et al [3] presented image compression hardware to reduce computational complexity. Others have proposed to optimize image computation by digital signal processor (DSP).…”

Section: Introductionmentioning

confidence: 99%

A Fast DCT Algorithm for Watermarking in Digital Signal Processor

Tsai

Yang

2017

Mathematical Problems in Engineering

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Discrete cosine transform (DCT) has been an international standard in Joint Photographic Experts Group (JPEG) format to reduce the blocking effect in digital image compression. This paper proposes a fast discrete cosine transform (FDCT) algorithm that utilizes the energy compactness and matrix sparseness properties in frequency domain to achieve higher computation performance. For a JPEG image of8×8block size in spatial domain, the algorithm decomposes the two-dimensional (2D) DCT into one pair of one-dimensional (1D) DCTs with transform computation in only 24 multiplications. The 2D spatial data is a linear combination of the base image obtained by the outer product of the column and row vectors of cosine functions so that inverse DCT is as efficient. Implementation of the FDCT algorithm shows that embedding a watermark image of 32 × 32 block pixel size in a 256 × 256 digital image can be completed in only 0.24 seconds and the extraction of watermark by inverse transform is within 0.21 seconds. The proposed FDCT algorithm is shown more efficient than many previous works in computation.

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Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT‐Based Image Compression

Cited by 12 publications

References 40 publications

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

A Fast DCT Algorithm for Watermarking in Digital Signal Processor

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