Optimizations of Two Compute-Bound Scientific Kernels on the SW26010 Many-Core Processor

Lin, James; Xu, Zhigeng; Nukada, Akira; Maruyama, Naoya; Matsuoka, Satoshi

doi:10.1109/icpp.2017.52

Cited by 17 publications

(13 citation statements)

References 16 publications

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“…In recent years, we have started to see projects that refactor WENO for heterogeneous architectures, such as refactoring WENO on the CPUCGPU Table 6 Execution time of the entire WENO that we port onto the CPE clusters with different optimize configurations (see Fig. 11 architecture [31] , refactoring the community atmosphere model [12] , phase field simulations of coarsening dynamics [30] , 10 m-core scalable fully-implicit solver for nonhydrostatic atmospheric dynamics [32] , molecular dynamics simulation [33] , sea ice model algorithms [34] , two compute-bound scientific kernels [35] , etc., on the Sunway TaihuLight system.…”

Section: Related Workmentioning

confidence: 99%

Heterogeneous parallel algorithm design and performance optimization for WENO on the Sunway Taihulight supercomputer

Huang

Han

Wang

et al. 2020

Tinshhua Sci. Technol.

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A Weighted Essentially Non-Oscillatory scheme (WENO) is a solution to hyperbolic conservation laws, suitable for solving high-density fluid interface instability with strong intermittency. These problems have a large and complex flow structure. To fully utilize the computing power of High Performance Computing (HPC) systems, it is necessary to develop specific methodologies to optimize the performance of applications based on the particular system's architecture. The Sunway TaihuLight supercomputer is currently ranked as the fastest supercomputer in the world. This article presents a heterogeneous parallel algorithm design and performance optimization of a high-order WENO on Sunway TaihuLight. We analyzed characteristics of kernel functions, and proposed an appropriate heterogeneous parallel model. We also figured out the best division strategy for computing tasks, and implemented the parallel algorithm on Sunway TaihuLight. By using access optimization, data dependency elimination, and vectorization optimization, our parallel algorithm can achieve up to 172× speedup on one single node, and additional 58× speedup on 64 nodes, with nearly linear scalability.

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Section: Related Workmentioning

confidence: 99%

Heterogeneous parallel algorithm design and performance optimization for WENO on the Sunway Taihulight supercomputer

Huang

Han

Wang

et al. 2020

Tinshhua Sci. Technol.

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“…In addition, there are multiple applications used in other disciplines that help double-buffering techniques to take samples (or transfer them between memories) while the data are processed in the same processor as Tan et al [33] suggest. This double-buffering technique has been used in image processing [39], paralleling processing [25] or ultrasound imaging methods [4]. However, our approach uses this double-buffering technique by adding a pipeline processing composed of timers, interruptions and a state machine.…”

Section: Data Acquisition Processesmentioning

confidence: 99%

Continuously Energy Consumption Measure Approach Using a DMA Double-Buffering Technique

Hernández

Muñoz

Barrero

et al. 2020

Preprint

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Measuring the consumption of electronic devices is a difficult and sensitive task. Data AcQuisition (DAQ) systems are often used to determine such consumption. In theory, measuring energy consumption is straightforward, just by acquiring current and voltage signals we can determine the consumption. However, a number of issues arise when a ne analysis is required. The main problem is that sampling frequencies have to be high enough to detect variations in the assessed signals over time. In that regard, some popular DAQ systems are based on RISC ARM processors for microcontrollers combined with Analog-Digital Converters (ADC) to meet the frequency acquisition requirements. The efficient use of the Direct Memory Access (DMA) modules combined with pipelined processing in the microcontroller allows to improve the sample rate overcoming the processing time and the internal communication protocol limitations. This paper presents a novel approach for high frequency energy measurement composed of a DMA rate improvement (data acquisition logic), a data processing logic and a low-cost hardware. The contribution of the paper is the combination of a double buffered signal acquisition mechanism and an algorithm that computes the device's energy consumption using parallel data processing. The combination of these elements enables a high-frequency (continuous) energy consumption measurement of an electronic device, improving the accuracy and reducing the cost of existing systems. We have validated our approach by measuring the energy consumed by basic circuits and Wireless Sensors Networks (WSNs) motes. The results indicate that the energy measurement error is less than 5%, and that the proposed method is suitable to measure WSN motes even during sleep cycles, enabling a better characterization of their consumption prole.

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“…Compared with recent research on regular problems on Sunway architecture, such as stencil [3], DNN [12], GEMM [18,27] and fully-implicit solver for nonhydrostatic atmospheric dynamics [66], our work presented in this paper is more complicated, as the irregularities from various matrix sparsity structures are dynamic and leveraging such irregularity is known to be more challenging [57,67].…”

Section: Related Workmentioning

confidence: 99%

swSpTRSV

Wang

Liu

Xue

et al. 2018

Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

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Sparse triangular solve (SpTRSV) is one of the most important kernels in many real-world applications. Currently, much research on parallel SpTRSV focuses on level-set construction for reducing the number of inter-level synchronizations. However, the out-of-control data reuse and high cost for global memory or shared cache access in inter-level synchronization have been largely neglected in existing work. In this paper, we propose a novel data layout called Sparse Level Tile to make all data reuse under control, and design a Producer-Consumer pairing method to make any inter-level synchronization only happen in very fast register communication. We implement our data layout and algorithms on an SW26010 many-core processor, which is the main buildingblock of the current world fastest supercomputer Sunway Taihulight. The experimental results of testing all 2057 square matrices from the Florida Matrix Collection show that our method achieves an average speedup of 6.9 and the best speedup of 38.5 over parallel level-set method. Our method also outperforms the latest methods on a KNC many-core processor in 1856 matrices and the latest methods on a K80 GPU in 1672 matrices, respectively.

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Optimizations of Two Compute-Bound Scientific Kernels on the SW26010 Many-Core Processor

Cited by 17 publications

References 16 publications

Heterogeneous parallel algorithm design and performance optimization for WENO on the Sunway Taihulight supercomputer

Heterogeneous parallel algorithm design and performance optimization for WENO on the Sunway Taihulight supercomputer

Continuously Energy Consumption Measure Approach Using a DMA Double-Buffering Technique

swSpTRSV

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