Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

Jeong, Hayeon; Lee, Hui-Dong; Park, Bonghyuk; Jang, Seunghyun; Kong, Sunwoo; Park, Changkun

doi:10.3390/app112411691

Cited by 4 publications

(1 citation statement)

References 11 publications

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“…In this study, as shown in Figure 1, a capacitive neutralization technique was utilized to ensure stability in the high gain PA [18][19][20]. In Figure 3, the equivalent half-circuit of the common-source stage of Figure 1 is shown.…”

Section: Determination Of Neutralization Capacitor Valuesmentioning

confidence: 99%

Ka-Band Three-Stack CMOS Power Amplifier with Split Layout of External Gate Capacitor for 5G Applications

Yang¹,

Lee²,

Jang³

et al. 2023

Electronics

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In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize power consumption in the driver stage. The layout of an external gate capacitor for the stacked power stage was split to maximize the performance of the power transistor. With the proposed split layout of the external capacitor, gain, output power, and power-added efficiency (PAE) were improved. Additionally, a capacitive neutralization technique was applied to the power and driver stages to ensure the stability and enhance the gain of the PA. The measured P1dB and the saturation power were 22.0 dBm and 23.3 dBm, respectively, while the peak PAE was 27.8% at 28.5 GHz.

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Section: Determination Of Neutralization Capacitor Valuesmentioning

confidence: 99%