2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) 2014
DOI: 10.1109/eptc.2014.7028368
|View full text |Cite
|
Sign up to set email alerts
|

Optimization of the wafer level molding process for high power device module

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2022
2022
2022
2022

Publication Types

Select...
1

Relationship

0
1

Authors

Journals

citations
Cited by 1 publication
(2 citation statements)
references
References 6 publications
0
2
0
Order By: Relevance
“…There are issues in molding process for WLCSP in semiconductor such as warpage, chips shift, void, stress concentration on chips and solder bumps [38][39][40]. Finite Element Method had been used to model the shrinkage caused by thermal mismatch of carrier and epoxy mold compound (EMC) which has resulted in chips shift and warpage [38][39].…”
Section: Molding Process For Cspmentioning
confidence: 99%
See 1 more Smart Citation
“…There are issues in molding process for WLCSP in semiconductor such as warpage, chips shift, void, stress concentration on chips and solder bumps [38][39][40]. Finite Element Method had been used to model the shrinkage caused by thermal mismatch of carrier and epoxy mold compound (EMC) which has resulted in chips shift and warpage [38][39].…”
Section: Molding Process For Cspmentioning
confidence: 99%
“…This is mainly contributed by coupling of coefficient of thermal expansion of different materials and mold flow effect [43]. Fluid-structure interaction (FSI) analysis and Computational Flow Dynamic (CFD) is used to simulate the EMC flow and the effects of solder bump arrangement on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated [40][41][42].…”
Section: Molding Process For Cspmentioning
confidence: 99%