2019
DOI: 10.1016/j.mejo.2019.01.008
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Optimization of short channel effect and external resistance on small size FinFET for different threshold voltage flavors and supply voltages

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Cited by 2 publications
(1 citation statement)
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“…In this study, V T extraction was followed the constant current methodology. To accelerate the process and circuit development in yield and reliability analysis in the nano-node era, the technology computer-aided design simulator is an appropriate choice as an assistant [23][24][25].…”
Section: Purpose Stress Methods Specificationsmentioning
confidence: 99%
“…In this study, V T extraction was followed the constant current methodology. To accelerate the process and circuit development in yield and reliability analysis in the nano-node era, the technology computer-aided design simulator is an appropriate choice as an assistant [23][24][25].…”
Section: Purpose Stress Methods Specificationsmentioning
confidence: 99%