Optimization of Processing and Modeling Issues for Thin-Film Solar Cell Devices; Annual Report, 3 February 1997-2 February 1998

Abstract

SummaryThe overall mission of the Institute of Energy Conversion is the development of thin film photovoltaic cells, modules, and related manufacturing technology and the education of students and professionals in photovoltaic technology. The objectives of this four-year NREL subcontract are to advance the state of the art and the acceptance of thin film PV modules in the areas of improved technology for thin film deposition, device fabrication, and material and device characterization and modeling, relating to solar cells based on CuInSe 2 and its alloys, on a-Si and its alloys, and on CdTe. CuInSe 2 -based Solar Cells High Bandgap CuInSe 2 AlloysCuInSe 2 has a bandgap of 1.0 eV and most Cu(InGa)Se 2 -based devices have absorber layers with Ga/(In+Ga) ≈ 0.25 which gives a bandgap of 1.15 eV and results in devices with open circuit voltages < 0.65V. Higher Ga concentrations to increase the Cu(InGa)Se 2 bandgap result in a trade-off of higher open circuit voltage and lower short circuit current which may allow increased cell efficiency. Further, module performance should be improved due to lower resistive losses, thinner ZnO with less optical loss and/or greater interconnect spacing with reduced associated arearelated losses.We have previously demonstrated Cu(InGa)Se 2 solar cells with 15% efficiency for Ga/(In+Ga) ≤ 0.5 or bandgap (Eg) ≤ 1.3 eV [101,102]. With higher bandgap a decrease in cell efficiency was shown to be caused by poor collection of light generated minority carriers in the Cu(InGa)Se 2 absorber layers and in this report, we have expanded the characterization of Cu(InGa)Se 2 devices with increasing Ga content and bandgap. Further, we have begun to investigate other CuInSe 2 -based alloy materials, CuInS 2 and Cu(InAl)Se 2 , which may provide alternative means to achieve improved device performance with Eg > 1.3 eV. Reduced Cu(InGa)Se 2 Deposition Temperature and ThicknessThere are many technical issues which need to be addressed to effectively enable the transfer of Cu(InGa)Se 2 deposition and device fabrication technology from the laboratory to manufacturing scale. In general, these issues provide a means to reduce thin film semiconductor process costs. Shorter deposition time can be achieved with reduced film thickness and increased deposition rate. Thinner absorber films reduce the total amount of material used and allow faster process throughput. The minimum thickness of the Cu(InGa)Se 2 absorber layer may be determined by the nucleation of the film to form a continuous layer or by the film morphology. From a device perspective, the minimum thickness may be determined by the minority carrier diffusion length and optical absorption coefficient of the Cu(InGa)Se 2 or the ability to incorporate optical confinement.Lower substrate temperature (T ss ) can lower processing costs by reducing thermally induced stress on the substrate, allowing faster heat-up and cool-down, and decreasing the heat load and stress on the entire deposition system. In addition, with lower substrate temperature, stress on ...

Optimization of Processing and Modeling Issues for Thin Film Solar Cell Devices Including Concepts for The Development of Polycrystalline Multijunctions: Annual Report; 24 August 1998-23 August 1999

“…They identified the possible effect of bias polarity on Cu electromigration. In our past reports [43], we have shown that there are at least two different degradation mechanisms, one affecting the junction (reducing V oc ) and one affecting the back contact (reducing FF and creating a blocking contact). More recently, IEC demonstrated that removing the contact from a degraded device and re-applying the contact restored the Ohmic back contact and FF but did not improve the V oc , thus separating the junction and contact degradation.…”

“…In Section 4.2.2 we will propose a chemical pathway for this process that brings together the chemical activity of species and the surface nature of the grain boundary mobility and diffusion processes. In the previous annual report, CdS-CdTe inter-diffusion measurements by both x-ray diffraction and comparison of starting to final CdS film thickness showed that the extent of CdS film consumption during post-deposition CdCl 2 treatment is least for CdTe films with the largest possible grain size and fewest crystallographic defects [46]. For a given CdTe film, the other parameters of the treatment, such as CdCl 2 partial pressure, oxygen partial pressure and reaction temperature determine the extent of CdS diffusion.…”

“…It is interesting to note that all four of these groups [39,40,41,42,43] studied devices in which the CdS/CdTe semiconductor layers were deposited at SCI, although there were likely to have been process changes over the 3 year period. Some groups applied their own contacts, others used devices completed at SCI with their contacts.…”

“…Film thickness was determined by optical absorption in the high-absorption region, from 400 to 450 nm. Pinholes in the CdS layer were by transmission optical microscopy assessed in the same way described in the previous annual report and were converted to a fractional area [44]. Table 4.1 below lists CdS effusion rate, film thickness, and fractional pinhole area for the central piece of the substrate array from ten sequential depositions targeting 80 nm film thickness.…”