Optimization of phase-locked loop circuits via geometric programming

Colleran, D. M.; Portmann, C.; Hassibi, Arjang; Crusius, C.; Mohan, S.S.; Boyd, Stephen; Lee, T.H.; Hershenson, M. del Mar

doi:10.1109/cicc.2003.1249422

Cited by 50 publications

(24 citation statements)

References 3 publications

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“…We refer to the prior method as the standard optimization. We demonstrate the effectiveness of our algorithm by using it to optimize the area of a two-stage CMOS operational amplifier and power for a voltage controlled oscillator, which have been used as validation vehicles in several prior related publications [10], [3] (Figure 4 and Figure 5). The two-stage amplifier circuit is made up of 8 transistors and the typical design metrics include gain, unity gain bandwidth, slew rate, common-mode rejection ratio, phase margin, as well as area.…”

Section: Resultsmentioning

confidence: 99%

An algorithm for exploiting modeling error statistics to enable robust analog optimization

Singh¹,

Lok²,

Ragab³

et al. 2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. Fitting over a large region can be grossly inaccurate, and in fact, poor posynomial fit can lead to failure to find a true feasible solution. On the other hand, fitting over smaller regions and then selecting the best region, incurs exponential complexity.In this paper, we advance a novel optimization strategy that circumvents these dueling problems in the following manner: by explicitly handling the error of the model in the course of optimization, we find a potentially suboptimal, but feasible solution. This solution subsequently guides a range-refinement process of our transistor models, allowing us to reduce the range of operating conditions and dimensions, and hence obtain far more accurate GP models.The key contribution is in using the available oracle (SPICE simulations) to identify solutions that are feasible with respect to the accurate behavior rather than the fitted model. The key innovation is the explicit link between the fitting error statistics and the rate of the error uncertainty set increase, which we use in a robust optimization formulation to find feasible solutions.We demonstrate the effectiveness of our algorithm on a two benchmarks: a two-stage CMOS operational amplifier and a voltage controlled oscillator designed in TSMC 0.18µm CMOS technology. Our algorithm is able to identify superior solution points producing uniformly better power and area values under gain constraint with improvements of up to 50% in power and 10% in area for the amplifier design. We also demonstrate that when utilizing the models with the same level of modeling error, our method yields solutions that meet the constraints while the violations for the standard method were as high as 45% and larger than 15% for several constraints.

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Section: Resultsmentioning

confidence: 99%

An algorithm for exploiting modeling error statistics to enable robust analog optimization

Singh¹,

Lok²,

Ragab³

et al. 2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Since the residual ISI dominates the other noise sources in HSLs by an order of magnitude [1], [2], in this work we focus on the optimization of the link signal-processing chain (transmit equalizer and driver, channel, receiver peaking amplifier), noting that the framework can be readily extended to the timing sub-system by using existing jitter-induced voltage noise models [2], [3] and PLL optimization formulations [8].…”

Section: System Level Modelmentioning

confidence: 99%

“…Once the circuit topology is chosen, designers have to generate equation-based models for each circuit in a way similar to previous examples of circuit-level equation-based optimization [5], [7], [8].…”

Section: Circuit Level Modelmentioning

confidence: 99%

Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example

Sredojevic

Stojanovic

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-speed links are particularly hard to analyze because of the complex interplay of device/circuit parasitics and channel filtering operation. In this paper we introduce optimization-based framework for link design-space exploration, connecting the link transmission quality and top-level filter settings with circuit power, sizing and biasing. We derive a special analytical discrete time representation that avoids the size explosion of the symbolic problem description improving the parsing and solver time by orders of magnitude and making this joint optimization possible in real-time. This robust and accurate problem formulation is derived in signomial form and is compatible with existing optimization approaches to circuit sizing. We demonstrate this optimization framework on a link design-space exploration example, investigating trade-offs between the transmit preemphasis and linear receiver equalizer and their impact on overall link power vs. data rate.

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“…Other problems in digital circuit design where GP plays a role include buffering and wire sizing Wong 1999, 2001a), sizing and placement (Chen et al 2000), yield maximization , Patil et al 2005, parasitic reduction (Qin and Cheng 2003), clock tree design (Vittal and Marek-Sadowska 1997), and routing (Borah et al 1997). Geometric programming has also been used for the design of nondigital circuits, e.g., analog circuits (Dawson et al 2001, Hershenson 2003, Hershenson et al 1998, Mandal and Visvanathan 2001, Vanderhaegen and Brodersen 2004, mixed-signal circuits (Colleran et al 2003, Hassibi and Hershenson 2002, Hershenson 2002, and RF (radio frequency) circuits Mohan et al 1999Mohan et al , 2000Xu et al 2004). Geometric programming has also been used in floorplanning, for both analog and digital circuits (Moh et al 1996).…”

Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Optimization of phase-locked loop circuits via geometric programming

Cited by 50 publications

References 3 publications

An algorithm for exploiting modeling error statistics to enable robust analog optimization

An algorithm for exploiting modeling error statistics to enable robust analog optimization

Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example

Digital Circuit Optimization via Geometric Programming

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