Optimization of high-level design edge detect filter for video processing system on FPGA

Alareqi, Mohammed; Elgouri, Rachid; Mateur, K.; Zemmouri, Abdelkarim; Mezouari, A.; Hlou, Laamari

doi:10.1109/isacv.2017.8054900

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…The block is fed with the core pixel values to be analyzed, as well as its neighboring pixels. The convolution operator is used in real-time applications for various edge detection algorithms [23], [24] and also edge filter for video processing system on reconfigurable platform [25], [26]. Get the O10 convolution resultant values based on this.…”

Section: Design Methodologymentioning

confidence: 99%

Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation

Kulkarni

2021

IJRES

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The bulks of image processing algorithms are either two-dimensional (2D) or confined by their very nature. As a result, the 2D convolution function has a large impact on picture processing requirements. The methodology of 2D convolution and media access control (MAC) design can also be used to perform a variety of image processing tasks, and even as picture blurring, softening, and feature extraction. The main goal of this research is to develop a more efficient MAC control block-based 2D convolution architecture. This 2D algorithm can be implemented in hardware using fewer modules, multipliers, adders, and control blocks, resulting in significant hardware savings and look up table (LUT) reductions. The simulations were run in Verilog, and the Xilinx Vertex family field programmable gate array (FPGA) was used to build and test them. The recommended 2D convolution architectural solution is significantly faster and consumes significantly less hardware resources than the traditional 2D convolution implementation. The proposed architecture will result in technology that saves a substantial amount of processing time when it comes to LUTs.

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Section: Design Methodologymentioning

confidence: 99%

Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation

Kulkarni

2021

IJRES

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“…This is due to the advantage that FPGAs have over other programmable devices. These advantages include: high clock rate, high number of operations per second, low cost, parallel processing, security, ability to interact with high or low interfaces and intellectual property (IP) preservation [2]. The Xilinx System Generator for Digital Signal Processing (DSP) is a tool that operates at a higher degree of abstraction, it is useful for those with familiar of MATLAB and Simulink.…”

Section: Introductionmentioning

confidence: 99%

Real Time Hardware Co-Simulation for Blind Image Separation Algorithm Using ZYNG 7000 & Xilinx System Generator

Mekhfioui¹

2020

IJETER

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The implementation of blind image processing required a solid background knowledge of the design and description languages of the material. This paper describes an effective method for implementing real-time blind image separation algorithms on hardware, without needing a comprehensive knowledge of hardware design and description languages(VHDL).This study concerns the separation of a mixture of images, with no prior information on the images or on the way they have been mixed together. It describes the methodology for implementing real-time DSP applications on FPGAs and the concept of hardware/software co-simulation of the blind image separation algorithm using MATLAB Simulink and Xilinx System Generator (XSG).The performance of efficient architectures is implemented on the ZYBO Z7 Zynq-7020 FPGA.

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An Exploration on Competent Video Processing Architectures

Tammana

Penumutchi

2023

2023 International Conference for Advancement in Technology (ICONAT)

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Optimization of high-level design edge detect filter for video processing system on FPGA

Cited by 4 publications

References 14 publications

Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation

Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation

Real Time Hardware Co-Simulation for Blind Image Separation Algorithm Using ZYNG 7000 & Xilinx System Generator

An Exploration on Competent Video Processing Architectures

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