Optimization of FPGA-based CNN accelerators using metaheuristics

Sait, Sadiq M.; Altakrouri, Mohammad; Shawahna, Ahmad

doi:10.1007/s11227-022-04787-8

Cited by 3 publications

(1 citation statement)

References 40 publications

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“…In the design of mainstream accelerators [31], to avoid high latency caused by accessing off-chip memory, weight parameters and intermediate calculation results are usually stored into on-chip BRAM memory in sequential order directly. However, when reading data, only one or two data can be read per clock according to the corresponding address.…”

Section: Optimization Of Data Reading Methodsmentioning

confidence: 99%

Research on Efficient CNN Acceleration Through Mixed Precision Quantization: A Comprehensive Methodology

He,

Liu,

Tahir

et al. 2023

IJACSA

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To overcome challenges associated with deploying Convolutional Neural Networks (CNNs) on edge computing devices with limited memory and computing resources, we propose a mixed-precision CNN calculation method on a Field Programmable Gate Array (FPGA). This approach involves a collaborative design encompassing both software and hardware aspects. Initially, we devised a CNN quantization method tailored for the fixed-point operation characteristics of FPGA, addressing the computational challenges posed by floating-point parameters. We introduce a bit-width strategy search algorithm that assigns bit-widths to each layer based on CNN loss variation induced by quantization. Through retraining, this strategy mitigates the degradation in CNN inference accuracy. For FPGA acceleration design, we employ a flow processing architecture with multiple Processing Elements (PEs) to support mixed-precision CNNs. Our approach incorporates a folding design method to implement shared PEs between layers, significantly reducing FPGA resource usage. Furthermore, we designed a data reading method, incorporating a register set buffer between memory and processing elements to alleviate issues related to mismatched data reading and computing speeds. Our implementation of the mixed-precision ResNet20 model on the Kintex-7 Eco R2 development board achieves an inference accuracy of 91.68% and a computing speed 4.27 times faster than the Central Processing Unit (CPU) on the CIFAR-10 dataset, with an accuracy drop of only 1.21%. Compared to a unified 16-bit FPGA accelerator design method, our proposed approach demonstrates an 89-fold increase in computing speed while maintaining similar accuracy.

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Section: Optimization Of Data Reading Methodsmentioning

confidence: 99%

Research on Efficient CNN Acceleration Through Mixed Precision Quantization: A Comprehensive Methodology

He,

Liu,

Tahir

et al. 2023

IJACSA

View full text Add to dashboard Cite

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Dataflow optimization with layer-wise design variables estimation method for enflame CNN accelerators

Chen,

Tan,

Zhang

et al. 2024

Journal of Parallel and Distributed Computing

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FPGA Implementation of Image Registration Using Accelerated CNN

Aydin

Bilge

2023

Sensors

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Background: Accurate and fast image registration (IR) is critical during surgical interventions where the ultrasound (US) modality is used for image-guided intervention. Convolutional neural network (CNN)-based IR methods have resulted in applications that respond faster than traditional iterative IR methods. However, general-purpose processors are unable to operate at the maximum speed possible for real-time CNN algorithms. Due to its reconfigurable structure and low power consumption, the field programmable gate array (FPGA) has gained prominence for accelerating the inference phase of CNN applications. Methods: This study proposes an FPGA-based ultrasound IR CNN (FUIR-CNN) to regress three rigid registration parameters from image pairs. To speed up the estimation process, the proposed design makes use of fixed-point data and parallel operations carried out by unrolling and pipelining techniques. Experiments were performed on three US datasets in real time using the xc7z020, and the xcku5p was also used during implementation. Results: The FUIR-CNN produced results for the inference phase 139 times faster than the software-based network while retaining a negligible drop in regression performance of under 200 MHz clock frequency. Conclusions: Comprehensive experimental results demonstrate that the proposed end-to-end FPGA-based accelerated CNN achieves a negligible loss, a high speed for registration parameters, less power when compared to the CPU, and the potential for real-time medical imaging.

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Optimization of FPGA-based CNN accelerators using metaheuristics

Cited by 3 publications

References 40 publications

Research on Efficient CNN Acceleration Through Mixed Precision Quantization: A Comprehensive Methodology

Research on Efficient CNN Acceleration Through Mixed Precision Quantization: A Comprehensive Methodology

Dataflow optimization with layer-wise design variables estimation method for enflame CNN accelerators

FPGA Implementation of Image Registration Using Accelerated CNN

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