Optimization of Collective Communication in Intra-cell MPI

Velamati, M. K.; Kumar, Arun; Jayam, Naresh; Senthilkumar, Ganapathy; Baruah, Pallav Kumar; Sharma, R.; Kapoor, Shakti; Srinivasan, Ashok

doi:10.1007/978-3-540-77220-0_45

Cited by 18 publications

(13 citation statements)

References 8 publications

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“…SPEs can use these effective addresses to DMA data from or to another SPE. As mentioned earlier, data can be transferred much faster between SPEs than between SPE and main memory [2], [5].…”

Section: Cell Architecture Overviewmentioning

confidence: 98%

Optimizing assignment of threads to SPEs on the cell BE processor

Sudheer

Nagaraju

Baruah

et al. 2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

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Section: Cell Architecture Overviewmentioning

confidence: 98%

Optimizing assignment of threads to SPEs on the cell BE processor

Sudheer

Nagaraju

Baruah

et al. 2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

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“…The impact on the overall execution time of the FIFO size is presented in the experiment results. Research in [17] also indicates the performance of EIB is dependent on the DMA size and the affinity. Multiple smaller DMA requests are slower than few longer ones.…”

Section: Fifo Size and Communication Patternmentioning

confidence: 96%

Exploiting Parallelism of MPEG-4 Decoder with Dataflow Programming on Multicore Processor

Chen

Chien

et al. 2010

International Symposium on Parallel and Distributed Processing With Applications

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Multicore processor provides large computation capability but also involves the complicate parallel programming. One of major considerations in parallel programming is the performance. Traditional design methodologies which usually start a design on a selected platform spend a lot of effort and time on tuning performance and debugging. When platform is changed even with different number of cores, considerable redesign effort is required. Hence a flexible design methodology is necessary.In this paper, a design methodology is presented for video codec, by using MPEG-4 SP decoder as an example, on multicore processor. The parallelisms of MPEG-4 decoder are discussed and exposed with the dataflow model. The dataflow model provides a high-level abstraction of underlying hardware. Computation and communication of MPEG-4 decoder are separated and represented as modules and channels, respectively. It is possible to synthesize the model targeting to either dedicate hardware or software on multiprocessor. To map the high level dataflow model to Cell processor, the mapping flow, including offline profiling, task allocation and runtime libraries, are developed. According to the profiling results, the allocation algorithm could allocate tasks on multiprocessors as balanced as possible. An efficient synchronization mechanism on Cell processor is also proposed. We also discuss the impact of the model and the mapping flow corresponding to decoding speed. The results show that the proposed methodology gets considerable performance boost when the number of cores is increased.

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“…In [14], [15], the researchers explored the hardware features on Cell processor and developed optimized collective operations. Comparing to traditional implementation, they achieved considerable speedup.…”

Section: B Hardware Approachesmentioning

confidence: 99%

Impact of reconfigurable hardware on accelerating MPI_Reduce

Gao

Schmidt

Sass

2010

2010 International Conference on Field-Programmable Technology

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This paper demonstrates the benefits and pit-falls of implementing the collective communication operation reduce in the reconfigurable resources of an FPGA device across a cluster of all-FPGA compute nodes. Specifically, the communication and computation semantics of the MPI_Reduce call from the de facto Message-Passing Interface have been implemented. Using a synthetic benchmark a cluster of 32 FPGA nodes with a 300 MHz PowerPC processor, custom high speed network, and reduce core is compared against a conventional commodity cluster with 3.2 GHz Xeon processors and Gigabit Ethernet. The design is customized to support performing many reduce operations on small datasets while minimizing the amount of on-chip resources used, which is an increasingly common demand from domain scientists. Speedups of ≈2× to ≈800× are reported over that of a commodity cluster for small datasets, which provides significant motivation to continue the investigation into supporting additional collective communication operations directly in hardware.

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Optimization of Collective Communication in Intra-cell MPI

Cited by 18 publications

References 8 publications

Optimizing assignment of threads to SPEs on the cell BE processor

Optimizing assignment of threads to SPEs on the cell BE processor

Exploiting Parallelism of MPEG-4 Decoder with Dataflow Programming on Multicore Processor

Impact of reconfigurable hardware on accelerating MPI_Reduce

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