Optimization of circuit partitioning in VLSI through classification algorithms

Abstract

In order to build complex digital logic circuits it is often essential to sub-divide multi million transistors design into manageable pieces. Circuit partitioning in VLSI, is one of the major area of research. There are many existing diverse algorithm to partition the circuit into sub circuits. This paper aims at circuit partitioning using two classification algorithms Decision Tree Algorithm and K-Nearest Neighbors Algorithm. These two algorithms were tested on a 3-bit Priority Encoder and a 4x2 SRAM sample circuits and implemented using VHDL. The tested result shows that the K-Nearest Neighbor algorithm yields better subcircuits than the Decision Tree Algorithm.

A study on various data mining algorithms pertaining to VLSI cell partitioning

“…The idea behind clustering algorithms is to group objects into subsets or clusters based on their relationship with each other [6]. Data in the same cluster will have related properties whereas those in different clusters will have unrelated properties [2].…”