Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

Dubey, Avaneesh K.; Nagaria, R. K.

doi:10.1016/j.mejo.2018.05.006

Cited by 44 publications

(11 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…the overall structure can be easily computed by using in a rectangle manner. it results very efficient layout respectively [6][7][8].…”

Section: Literature Survey Array Multipliermentioning

confidence: 97%

High Speed and Efficient Wallace Tree Multiplier for Dsp Applications

Abdullah¹

2020

JVCS

View full text Add to dashboard Cite

Multiplier is one of the key and fundamental block in the many applications such as DSP, signal processing etc. In numerous occasions multipliers plays a prominent role to decide the system performance. Out of the several multipliers wallace tree multiplier is one of reliable and occupies the minimal space in digital applications. This work describes the designing of the high performance 8 bit wallace tree multiplier using compressor technique. The multiplier were simulated and estimated its performance using the Vivado.

show abstract

“…the overall structure can be easily computed by using in a rectangle manner. it results very efficient layout respectively [6][7][8].…”

Section: Literature Survey Array Multipliermentioning

confidence: 97%

High Speed and Efficient Wallace Tree Multiplier for Dsp Applications

Abdullah¹

2020

JVCS

View full text Add to dashboard Cite

show abstract

“…Comparator has to be designed with high accuracy providing high slew rate and gain, since the decision of 0 logic and 1 logic should be passed quickly for data converters [17,18].Dynamic latch comparator shown in the Fig.3 has a setback of limited to only two stages and to reduce delay an extra stage is introduced with more area and a higher power consumption [19,20,21,22]. Conventional comparator is shown in the fig.4 [23].…”

Section: Existing Designsmentioning

confidence: 99%

1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

2019

IJITEE

View full text Add to dashboard Cite

Advanced medical equipments embedded with the sensors, analog to digital converters (ADC) and other equipment. Gain amplifier and the comparator are key blocks in ADCs improvement. Comparator is the key element in achieving a low offset and high slew ratein the ADCs, in addition power and speed optimizationdesigns are preferred. To achieve high speed and low power a modified architecture of a comparator is introduced. A 5V two stage comparator is designed to meet the specifications as, offset value <8.4mV, power dissipation <1.5mW and slew rate>14.68V/µS. Cadence Virtuoso tools and SCL 0.18 µm technology parameters are used for design. Designed comparator shows improved slew rate and power consumption in comparison with the existing comparators

show abstract

“…where, g m is the effective trans-conductance and R out is the effective output resistance [1,13]. Looking at the output node V out the resistance R B can be calculated as given in Equation 1:…”

Section: Mathematical Analysismentioning

confidence: 99%

“…and accuracy, sturdily depend upon the comparator's capability to detect the smallest voltage levels [11,12]. The op-amp comparators with a high slew rate and high gain with high accuracy are to be designed in order to attain these excellent parameters in data converters [13,14]. A modified architecture is proposed in this paper, which suggests useful data information in understanding the performance of op-amp comparators.…”

Section: Introductionmentioning

confidence: 99%

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Khatak

Kumar

Dhull

2018

JLPEA

View full text Add to dashboard Cite

A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

show abstract

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

Cited by 44 publications

References 11 publications

High Speed and Efficient Wallace Tree Multiplier for Dsp Applications

High Speed and Efficient Wallace Tree Multiplier for Dsp Applications

1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Contact Info

Product

Resources

About