Optimization for full-chip process of 130-nm technology with 248-nm DUV lithography

Abstract

We estimated the process margins of various cell structures and process problems for full chip process under extreme resolution limit of exposure tool. Therefore, optimizing off axis illumination (OAI) condition for various structures obtained the fme pattern and wider process margin using simulation and experiment. From our experiment, we should use as higher numerical aperture (NA), smaller R and smaller r as possible to reduce critical dimension (CD) difference between dense and isolated patterns. Process margins are obtained more than 8% exposure latitude (EL) and 0.5 tin depth of focus (DOF) for each cell. However, we can consider using of attenuated phase shift mask (PSM) to improve the exposure and DOF margin. We fmd that real full chip process induces the critical problems such as isolated line (I/L) and space (L'S) pattern variation due to lens aberration, partial coherence effect, mask error effect, and optical proximity effect. These effects play a role to determine the design rule of cell and periphery structures. In spite of good lens quality, variation of I/L and US pattern for various exposure conditions is almost 4Onm or more compared to line and space (L/S) pattern. These phenomena are becoming the critical issue to fulfill the full chip process of l3Onm lithography. By optimizing mask error effect, isolated and dense pattern bias (ID bias), and OAI, we can achieve l3Onm technology with 248nm KrF lithography.

Sub-120-nm technology compatibility of attenuated phase-shift mask in KrF and ArF lithography

“…EL oc CAI(A,P) x R(P) (2) ELocA( CAI(A,P)AatBIM) (3) Here, CAI is the contrast of aerial image, R is the function ofresist, A is the efficiency of 1St order light and P is thepitch size of mask pattern. EL is the function of aerial image contrast and resist process.…”