OPTIMIST: state minimization for optimal 2-level logic implementation

Abstract

We present a novel method for state minimization of incompletely-specified finite state machines. Where classic methods simply minimize the number of states, ours directly addresses the implementation's logic complexity, and produces an exactly optimal implementation under input encoding. The method incorporates optimal "state mapping", i.e., the process of reducing the symbolic next-state relation which results from state splitting to an optimal conforming symbolic function. Further, it offers a number of convenient sites for applying heuristics to reduce time and space complexity, and is amenable to implementation based on implicit representations. Although our method currently makes use of an input encoding model, we believe it can be extended smoothly to encompass output encoding as well.1 Introduction State minimization is the problem of finding a machine realizing the input/output behaviour of a given FSM, with fewer internal states [11,17,12]. This is an important step in sequential synthesis: implementing unminimized FSM's often leads to considerably larger and/or slower implementations. However, it is well known that the classic formulation for state minimization expresses a heuristic -reducing the number of states only tends to decrease logic complexity. Early on, Hartmanis observed [9] that this heuristic sometimes fails; realizations having more states may be simpler to implement. Moreover, there may be many minimum-state realizations of a given FSM, and their logic complexity can vary significantly [18,16]. Hence, simply targeting any minimum-state solution is insufficient.The major contribution of this paper is a state minimization method which, in contrast to existing ones, directly targets logic complexity. In particular, we define and solve the optimal state minimization problem, that of finding for a given FSM a realization having minimum 2-level logic complexity over all realizations.Classic sequential synthesis comprises several steps: state minimization, state encoding, 2-level logic minimization, multi-level optimization and technology mapping. Each step has traditionally been treated as an isolated problem, which limits early steps most * This research was funded in part by NSF CAREER Award MIP-9501880 and by an Alfred P. Sloan Research Fellowship.severely. In [7], a key insight into optimal state encoding was presented: symbolic logic minimization can be performed concurrently with state encoding. More recent methods for optimal encoding have been developed [20,8] based on the same insight, but yielding even better results.We borrow this insight, and take it one step further: symbolic logic minimization is performed concurrently with both state minimization and state encoding. Our method is cast as a unique form of generalized prime implicant minimization [8]. Specifically, symbolic prime implicants are generated, and a binate covering problem is formed and solved, yielding a reduced machine and logic cover.Our paper offers a novel theoretical framework for formulating and solving...

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

“…Concurrent state minimization and state encoding was suggested in [2], [7], [10], [18], [10] with little success. Hallbauer et al [10] proposed a method for asynchronous circuits based on pseudo-dichotomies trying to perform state minimization while heuristically reducing the encoding length, with no reported results.…”

“…Although reasonably efficient, the experimental results on a subset of the MCNC benchmarks do not show improvements over a serial synthesis strategy. Fuhrer et al proposed OPTIMIST [7], a concurrent state minimization and state encoding algorithm for two-level logic implementation. It provides an exact solution to FSM optimization for two-level logic implementation.…”

OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic

“…OPTIMIST [3] was one attempt to address this issue broadly for technology-independent logic synthesis, by attacking the problem of optimal state minimization for incompletely-specified synchronous FSM's. The problem is defined as selecting the reduced machine that has the best 2-level logic implementation over all possible state mini-£ This research was funded in part by NSF Award CCR-97-34803.…”