Optimised memory allocation for less false abortion and better performance in hardware transactional memory

Li, Xiuhong; Altenbek, Gulila

doi:10.1080/17445760.2019.1605605

Cited by 2 publications

(1 citation statement)

References 8 publications

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“…In addition to the abortions caused by invalidation message, cache line eviction will also force hardware transaction to abort. The work by Li and Gulila (2019) addresses the false abortion problem through redesigning the memory allocator to place objects that are likely to be accessed together by different threads in separated cache lines. Despite false sharing among multiple threads, conflict misses (Hill and Smith 1989) may even result in consistent abortions in a single-threaded execution.…”

Section: Memory Allocations Impactsmentioning

confidence: 99%

A survey on optimizations towards best-effort hardware transactional memory

Lü

Wang

et al. 2020

CCF Trans. HPC

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Transactional memory has been attracting increasing attention in recent years, and it provides optimistic concurrency control schemes for shared-memory parallel programs. The rapid development and wide adoption of transactional memory make this programming paradigm promising for achieving breakthroughs in massively parallel computing. There has been a large number of discussions towards transactional memory systems, which aimed at providing relatively simple and intuitive synchronization construction for shared-memory parallel programs without sacrificing performance. Hardware transactional memory (HTM) has become commercially available in mainstream processors, however, due to several inherent architectural limitations that will abort hardware transactions, such as cache overflows, context switches, hardware as well as software exceptions, etc., nowadays HTM systems come in a best-effort way, which necessitates the adoption of a software fallback path to ensure forward progress. In this paper, we survey state-of-the-art software-side optimizations for best-effort hardware transaction system, as well as several novel performance tuning techniques. Research efforts about joint usage of HTM and non-volatile memory (NVM) are also discussed.

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Section: Memory Allocations Impactsmentioning

confidence: 99%

A survey on optimizations towards best-effort hardware transactional memory

Lü

Wang

et al. 2020

CCF Trans. HPC

View full text Add to dashboard Cite

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Loop Selection for Multilevel Nested Loops Using a Genetic Algorithm

Nie

Zhou

Huang

et al. 2021

Mathematical Problems in Engineering

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Loop selection for multilevel nested loops is a very difficult problem, for which solutions through the underlying hardware-based loop selection techniques and the traditional software-based static compilation techniques are ineffective. A genetic algorithm- (GA-) based method is proposed in this study to solve this problem. First, the formal specification and mathematical model of the loop selection problem are presented; then, the overall framework for the GA to solve the problem is designed based on the mathematical model; finally, we provide the chromosome representation method and fitness function calculation method, the initial population generation algorithm and chromosome improvement methods, the specific implementation methods of genetic operators (crossover, mutation, and selection), the offspring population generation method, and the GA stopping criterion during the GA operation process. Experimental tests with the SPEC2006 and NPB3.3.1 standard test sets were performed on the Sunway TaihuLight supercomputer. The test results indicated that the proposed method can achieve a speedup improvement that is superior to that by the current mainstream methods, which confirm the effectiveness of the proposed method. Solving the loop selection problem of multilevel nested loops is of great practical significance for exploiting the parallelism of general scientific computing programs and for giving full play to the performance of multicore processors.

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Optimised memory allocation for less false abortion and better performance in hardware transactional memory

Cited by 2 publications

References 8 publications

A survey on optimizations towards best-effort hardware transactional memory

A survey on optimizations towards best-effort hardware transactional memory

Loop Selection for Multilevel Nested Loops Using a Genetic Algorithm

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