IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)
DOI: 10.1109/isvlsi.2006.70
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Optimisation of the SHA-2 Family of Hash Functions on FPGAs

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Cited by 88 publications
(56 citation statements)
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“…The implementation overhead of our proposed protocol is much less than traditional cryptographic modules. For example, robust hashing implementation of SHA-2 as listed in Table IV requires at least 5492 LUTs of a Virtex-II FPGA [27] and it takes 68 clock cycles to evaluate. This overhead will occur on the top of the clock cycles required for PUF evaluation.…”
Section: Hardware Implementationmentioning
confidence: 99%
“…The implementation overhead of our proposed protocol is much less than traditional cryptographic modules. For example, robust hashing implementation of SHA-2 as listed in Table IV requires at least 5492 LUTs of a Virtex-II FPGA [27] and it takes 68 clock cycles to evaluate. This overhead will occur on the top of the clock cycles required for PUF evaluation.…”
Section: Hardware Implementationmentioning
confidence: 99%
“…Another implementation in [9] which consumed 1373 slices for SHA-256 core, and 2726 slices for SHA-512 core with no power results provided. The implementation of [10] used ASIC core for 8-bit SHA-256 core.…”
Section: Related Workmentioning
confidence: 99%
“…In [23], [24] the whole SHA-2 family is implemented in FPGAs and compared in terms of area, frequency of operation and throughput. Some other works [25], [26], [27] provide further comparisons of FPGA-based implementations of hash functions. Also, some optimizations based on pipelining, loop unrolling, operation rescheduling and hardware reutilization are proposed in [28], [29].…”
Section: Related Workmentioning
confidence: 99%