Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler
Ruibing Dong,
Shinsuke Hara,
Mohamed H. Mubarak
et al.
Abstract:This paper presents the design and measurements of a 215-252 GHz 40 nm bulk CMOS frequency doubler with a 6.8 dBm deliverable peak output power and a conversion gain of 11.8 dB. The designed chip is composed of a 28.5 dB gain 6-stages 110 GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum… Show more
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